Minjae Lee
Orcid: 0000-0003-1500-1404Affiliations:
- Gwangju Institute of Science and Technology (GIST), School of Electrical Engineering and Computer Science, Gwangju, South Korea
- University of California, Los Angeles (UCLA), Los Angeles, CA, USA (PhD 2008)
According to our database1,
Minjae Lee
authored at least 53 papers
between 2006 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC.
IEEE J. Solid State Circuits, July, 2025
A 16.8 fJ/c-s 8 b 500 MS/s Asynchronous Three-Comparator SAR ADC With Background Comparator-Swapping Offset Calibration in 28 nm CMOS LPP.
IEEE Access, 2025
2024
A Fully Differential Direct Sampling Touch Screen Readout With a Touch Vector Calibration for Ultrathin Organic Light-Emitting Diode Display.
IEEE Trans. Ind. Electron., September, 2024
IEEE Access, 2024
Piezoresistance of Silicon Nanowires for Sensing Applications: Optimizing Nanowire Parameters From Electrical and Mechanical Perspectives.
IEEE Access, 2024
9.9 A 2.72fJ/conv 13b 2MS/s SAR ADC Using Dynamic Capacitive Comparator with Wide Input Common Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 0.9V Self-Referenced Resistor-Based Temperature Sensor With -0.62/+0.81°C (3σ) Inaccuracy.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
An 8-bit 1.24 mW Sub-1ps DNL Sub-1V Supply Inverter-Based Phase Interpolator Using a PVT-Tracking Adaptive-Bias Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Self Capacitance Mismatch Calibration Technique for Fully-Differential Touch Screen Panel Self Capacitance Sensing System.
Sensors, April, 2023
A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration.
IEEE Access, 2023
2022
A Background M-Channel Time-Interleaved ADC Calibration for Multilevel Modulations Based on the Probability Density Function Difference and a Greedy Algorithm.
IEEE Trans. Signal Process., 2022
A Greedy Search Approach for Time-Interleaved ADCs Calibration Based on NRZ Input Patterns.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications.
IEEE Access, 2022
2021
5th-Order Continuous-Time Low-Pass Filter Achieving 56 MHz Bandwidth 30.5 dBm IIP3 With a Novel Low-Distortion Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Foreground Calibration for M-Channel Time-Interleaved Analog-to-Digital Converters Based on Genetic Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A New Measurement Method for High Voltages Applied to an Ion Trap Generated by an RF Resonator.
Sensors, 2021
2020
All-Digital Bandwidth Mismatch Calibration of TI-ADCs Based on Optimally Induced Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications.
IEEE Access, 2020
An Efficient Reconfigurable RF-DC Converter With Wide Input Power Range for RF Energy Harvesting.
IEEE Access, 2020
A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications.
IEEE Access, 2020
An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO.
IEEE Access, 2020
Calibration of M-Channel Time-Interleaved Analog-to-Digital Converters Based on Curve Fitting.
Proceedings of the International SoC Design Conference, 2020
2019
A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on-chip LDO regulator for 5G applications.
Int. J. Circuit Theory Appl., 2019
2018
A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator With Temperature Compensation and 15-dB Noise Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Highly Linear, AEC-Q100 Compliant Signal Conditioning IC for Automotive Piezo-Resistive Pressure Sensors.
IEEE Trans. Ind. Electron., 2018
A 39.5-dB SNR, 300-Hz Frame-Rate, 56 × 70-Channel Read-Out IC for Electromagnetic Resonance Touch Panels.
IEEE Trans. Ind. Electron., 2018
A 3.9 mW Bluetooth Low-Energy Transmitter Using All-Digital PLL-Based Direct FSK Modulation in 55 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique.
Sensors, 2018
A Design of Small Area, 0.95 mW, 612-1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications.
Sensors, 2018
Design of a Low-Power, Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology.
Sensors, 2018
A 6-bit 4 MS/s 26fJ/conversion-step segmented SAR ADC with reduced switching energy for BLE.
Int. J. Circuit Theory Appl., 2018
Design of MEMS-based SiO2 Waveguides on Quartz Substrate for Evanescent Field-based Saturable Absorbers.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2018
2017
An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Microelectron. J., 2017
Quantizer-less proportional path fractional-N digital PLL with a low-power high-gain time amplifier and background multi-point spur calibration.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
Sensors, 2016
A 12 bit 250 MS/s 28 mW +70 dB SFDR non-50% RZ DAC in 0.11 µm CMOS using controllable RZ window for wireless SoC integration.
Microelectron. J., 2016
2015
A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Low Flicker Noise, Odd-Phase Master LO Active Mixer Using a Low Switching Frequency Scheme.
IEEE J. Solid State Circuits, 2015
2014
IEICE Electron. Express, 2014
A 3 kHz flicker noise corner, odd-phase active mixer for direct conversion receivers.
Proceedings of the ESSCIRC 2014, 2014
A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A low-power reference buffer with high PSRR and low crosstalk for time-interleaved ADCs.
IEICE Electron. Express, 2013
2012
IEICE Electron. Express, 2012
2009
A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution.
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
2008
A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue.
IEEE J. Solid State Circuits, 2008
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006