Sinho Lee

Orcid: 0009-0007-7921-5766

According to our database1, Sinho Lee authored at least 8 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Pattern-Dependent Pulse Filtering Technique for Low-Jitter Injection-Locked CDR in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., February, 2026

A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference.
IEEE J. Solid State Circuits, February, 2026

2025
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver With Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

2024
A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024

A 16-30Gb/s 1.03pJ/b Referenceless Baud-Rate CDR with Integrated Pattern Decoding Technique for Fast Frequency Acquisition.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023
A 0.9V Self-Referenced Resistor-Based Temperature Sensor With -0.62/+0.81°C (3σ) Inaccuracy.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023


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