Jintae Kim
This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.
Bibliography
2026
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026
A 1.5-GS/s 7-bit Charge-Injection SAR ADC Using a PVT-Tracking 1-bit Metastability Detector.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2026
2025
Quantum, 2025
A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique.
IEEE Solid State Circuits Lett., 2025
A Temperature and Common-Mode Insensitive 8.6 bit 1.5 GS/s Pipelined SAR ADC Using Complementary Dynamic Amplifier in 28 nm CMOS.
IEEE Access, 2025
A 17.4fJ/conv.-step, 202µm<sup>2</sup>, 1.5GS/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS.
IEEE J. Solid State Circuits, March, 2024
Optimal Switching Method Using Variable Additional On-Time Control for CRM-Operated Multicell Series-Parallel Converter.
IEEE Trans. Ind. Electron., 2024
Proceedings of the Computer Vision - ECCV 2024, 2024
A Single-Channel 3.1GS/s 45dB SNDR Pipelined ADC using Amplify-and-Select Structure in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
Comprehensive investigation of corrugated fiberboard boxes with edge vents for ambient loading of chinese cabbage: Part I - Computational fluid dynamics simulation and experimental validation.
Comput. Electron. Agric., December, 2023
A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers.
IEEE Access, 2023
BiFormer: Learning Bilateral Motion Estimation via Bilateral Transformer for 4K Video Frame Interpolation.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
A 7.9-ENOB 1. 5GS/s Common-Mode and Temperature Insensitive Pipelined-SAR ADC with an On-Chip Temperature-Sensor-Based Stage-Gain Compensation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 7GHz ERBW 1.1GS/s 6-bit PVT Tolerant Asynchronous CI-SAR with only 8.5fF Input Capacitance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2021
IEEE J. Solid State Circuits, 2021
A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration.
IEEE Access, 2021
An 8-bit Ring-Amplifier Based Mixed-Signal MAC Circuit With Full Digital Interface and Variable Accumulation Length.
IEEE Access, 2021
Proceedings of the 93rd IEEE Vehicular Technology Conference, 2021
1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2021
2020
Dynamic TDD Systems for 5G and Beyond: A Survey of Cross-Link Interference Mitigation.
IEEE Commun. Surv. Tutorials, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A 20-kHz~16-MHz Programmable-Bandwidth 4th Order Active Filter Using Gain-Boosted Opamp With Negative Resistance in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the 89th IEEE Vehicular Technology Conference, 2019
Millimeter-Wave Radar and RGB-D Camera Sensor Fusion for Real-Time People Detection and Tracking.
Proceedings of the 7th International Conference on Robot Intelligence Technology and Applications, 2019
A Robust Client-Server Architecture for Map Information Processing and Transmission for Distributed Visual SLAM.
Proceedings of the 7th International Conference on Robot Intelligence Technology and Applications, 2019
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
A Digitally-Calibrated 70.98dB-SNDR 625kHz-Bandwidth Temperature-Tolerant 2<sup>nd</sup>-order Noise-Shaping SAR ADC in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE Trans. Wirel. Commun., 2018
Eigendecomposition-Based GFDM for Interference-Free Data Transmission and Pilot Insertion for Channel Estimation.
IEEE Trans. Wirel. Commun., 2018
A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V.
IEEE J. Solid State Circuits, 2018
A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector.
IEEE J. Solid State Circuits, 2018
2017
IEICE Trans. Electron., 2017
IEICE Trans. Electron., 2017
IEEE Commun. Lett., 2017
Proceedings of the 86th IEEE Vehicular Technology Conference, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Proceedings of the 27th IEEE Annual International Symposium on Personal, 2016
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 14 nm FinFET 128 Mb SRAM With V<sub>MIN</sub> Enhancement Techniques for Low-Power Applications.
IEEE J. Solid State Circuits, 2015
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
2014
Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A Calibration Technique for Multibit Stage Pipelined A/D Converters via Least-Squares Method.
IEEE Trans. Instrum. Meas., 2013
A low-power reference buffer with high PSRR and low crosstalk for time-interleaved ADCs.
IEICE Electron. Express, 2013
2012
Comput. Appl. Eng. Educ., 2012
Proceedings of the Computer Applications for Bio-technology, Multimedia, and Ubiquitous City, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
2009
Proceedings of the Ninth International Conference on Quality Software, 2009
2008
DRAMA: A framework for domain requirements analysis and modeling architectures in software product lines.
J. Syst. Softw., 2008
2007
A Large-Swing Transformer-Boosted Serial Link Transmitter With > V<sub>DD</sub> Swing.
IEEE J. Solid State Circuits, 2007
Device-circuit co-optimization for mixed-mode circuit design via geometric programming.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
J. Syst. Softw., 2006
Improving use case driven analysis using goal and scenario authoring: A linguistics-based approach.
Data Knowl. Eng., 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Proceedings of the IEEE 2nd International Conference on Mobile Adhoc and Sensor Systems, 2005
2004
Ind. Manag. Data Syst., 2004
Proceedings of the 36th conference on Winter simulation, 2004
A Linguistics-Based Approach for Use Case Driven Analysis Using Goal and Scenario Authoring.
Proceedings of the Natural Language Processing and Information Systems, 2004
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
A Method and Tool Support for Variant Requirements Analysis: Goal and Scenario Based Approach.
Proceedings of the 11th Asia-Pacific Software Engineering Conference (APSEC 2004), 30 November, 2004
2000
Proceedings of the 7th Asia-Pacific Software Engineering Conference (APSEC 2000), 2000
1999
Proceedings of the 6th Asia-Pacific Software Engineering Conference (APSEC '99), 1999