Minoru Okamoto

According to our database1, Minoru Okamoto authored at least 5 papers between 1995 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems.
IEEE J. Solid State Circuits, 2009

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2005
160-Gbit/s Full Channel Optical Time-Division Demultiplexer Based on SOA-Array Integrated PLC and Its Application to OTDM Transmission Experiment.
IEICE Trans. Commun., 2005

1996
An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor.
IEEE J. Solid State Circuits, 1996

1995
An equalizing and channel coding processor for GSM terminals.
Proceedings of the 1995 International Conference on Acoustics, 1995


  Loading...