Tomoyuki Yamase

According to our database1, Tomoyuki Yamase authored at least 5 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems.
IEEE J. Solid State Circuits, 2009

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006
Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz.
IEEE J. Solid State Circuits, 2006

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver.
IEEE J. Solid State Circuits, 2006

2003
A widely tunable CMOS Gm-C filter with a negative source degeneration resistor transconductor.
Proceedings of the ESSCIRC 2003, 2003


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