Mohamed Nekili

According to our database, Mohamed Nekili authored at least 15 papers between 1993 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects.

Falah R. Awwad, Mohamed Nekili, Mohamad Sawan

Int. J. Circuit Theory Appl., 2012

2008

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects.

Falah R. Awwad, Mohamed Nekili, Venkatanarayana Ramachandran, Mohamad Sawan

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2005

Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree.

Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms.

Alexandre Landry, Mohamed Nekili, Yvon Savaria

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Optimal partitioning of globally asychronous locally synchronous processor arrays.

Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

Adaptive wire adjustment for bounded skew Clock Distribution Network.

Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.

Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.

Bill Pontikakis, Mohamed Nekili

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.

Falah R. Awwad, Mohamed Nekili

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

Minimizing process-induced skew using delay tuning.

Mohamed Nekili, Yvon Savaria, Guy Bois

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999

Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI.

Mohamed Nekili, Yvon Savaria, Guy Bois

IEEE J. Solid State Circuits, 1999

1998

Design of Clock Distribution Networks in Presence of Process Variations.

Mohamed Nekili, Yvon Savaria, Guy Bois

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.

Mohamed Nekili, Guy Bois, Yvon Savaria

IEEE Trans. Very Large Scale Integr. Syst., 1997

1994

A Fast Low-Power Driver for Long Interconnections in VLSI Systems.

Mohamed Nekili, Yvon Savaria, Guy Bois

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.

Mohamed Nekili, Yvon Savaria

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993