Syed Rafay Hasan
Orcid: 0000-0003-0183-8086
According to our database1,
Syed Rafay Hasan
authored at least 87 papers
between 2004 and 2024.
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Bibliography
2024
System Integration of Xilinx DPU and HDMI for Real-Time Inference in PYNQ Environment With Image Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
FM-ModComp: Feature Map Modification and Hardware-Software Co-Comparison for secure hardware accelerator-based CNN inference.
Microprocess. Microsystems, July, 2023
StAIn: Stealthy Avenues of Attacks on Horizontally Collaborated Convolutional Neural Network Inference and Their Mitigation.
IEEE Access, 2023
Mitigation of Rowhammer Attack on DDR4 Memory: A Novel Multi-Table Frequent Element Algorithm Based Approach.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Integrating Gstreamer with Xilinx's ZCU 104 Edge Platform for Real-Time Intelligent Image Enhancement.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023
Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
2L-3W: 2-Level 3-Way Hardware-Software Co-verification for the Mapping of Convolutional Neural Network (CNN) onto FPGA Boards.
SN Comput. Sci., 2022
Edge Intelligence in Mobile Nodes: Opportunistic Pipeline via 5G D2D for On-site Sensing.
Proceedings of the 96th Vehicular Technology Conference, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the 14th IFIP Wireless and Mobile Networking Conference, 2022
Framework to Benchmark CNNs (FaBCNN) for Processing Real-Time HD Video Streams on FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Hardening Hardware Accelerartor Based CNN Inference Phase Against Adversarial Noises.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
InTrust-IoT: Intelligent Ecosystem based on Power Profiling of Trusted device(s) in IoT for Hardware Trojan Detection.
Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021
SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Formal Reliability Analysis of an Integrated Power Generation System Using Theorem Proving.
IEEE Syst. J., 2020
SIMCom: Statistical sniffing of inter-module communications for runtime hardware trojan detection.
Microprocess. Microsystems, 2020
MacLeR: Machine Learning-based Run-Time Hardware Trojan Detection in Resource-Constrained IoT Edge Devices.
CoRR, 2020
Collaborative Pipeline Using Opportunistic Mobile Resources via D2D for Computation-Intensive Tasks.
CoRR, 2020
CoRR, 2020
Fusion-On-Field Security and Privacy Preservation for IoT Edge Devices: Concurrent Defense Against Multiple Types of Hardware Trojan Attacks.
IEEE Access, 2020
Deployment of Object Detection Enhanced with Multi-label Multi-classification on Edge Device.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
Integr., 2019
2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Deep Learning Architecture (DLA) onto FPGA Boards.
CoRR, 2019
A Scalable Multilabel Classification to Deploy Deep Learning Architectures For Edge Devices.
CoRR, 2019
A Stealthy Hardware Trojan Exploiting the Architectural Vulnerability of Deep Learning Architectures: Input Interception Attack (IIA).
CoRR, 2019
SIMCom: Statistical Sniffing of Inter-Module Communications for Run-time Hardware Trojan Detection.
CoRR, 2019
MulNet: A Flexible CNN Processor With Higher Resource Utilization Efficiency for Constrained Devices.
IEEE Access, 2019
(HIADIoT): Hardware Intrinsic Attack Detection in Internet of Things; Leveraging Power Profiling.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Intrusion Detection in PLC-Based Industrial Control Systems Using Formal Verification Approach in Conjunction with Graphs.
J. Hardw. Syst. Secur., 2018
Runtime hardware Trojan monitors through modeling burst mode communication using formal verification.
Integr., 2018
CoRR, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
A Novel Framework to Introduce Hardware Trojan Monitors using Model Checking Based Counterexamples: Inspired by Game Theory.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Behavior profiling of power distribution networks for runtime hardware trojan detection.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Area efficient soft error tolerant RISC pipeline: Leveraging data encoding and inherent ALU redundancy.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A novel correlation power analysis attack on PIC based AES-128 without access to crypto device.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Formal verification of demand response based home energy management systems in smart grids.
Proceedings of the 2017 IEEE Innovative Smart Grid Technologies - Asia, 2017
Motion artifact reduction from PPG signals during intense exercise using filtered X-LMS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous.
Integr., 2016
Grouped through silicon vias for lower <i>L</i>d<i>i</i>/d<i>t</i> drop in three-dimensional integrated circuit.
IET Circuits Devices Syst., 2016
Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification.
J. Electron. Test., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Synchronously triggered GALS design templates leveraging QDI asynchronous interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Translating circuit behavior manifestations of hardware Trojans using model checkers into run-time Trojan detection monitors.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
2015
Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits.
Microelectron. Reliab., 2015
Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection.
Proceedings of the Nordic Circuits and Systems Conference, 2015
Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
Timing variation aware dynamic digital phase detector for low-latency clock domain crossing.
IET Circuits Devices Syst., 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Modeling, analyzing, and abstracting single event transient propagation at gate level.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Yield aware inter-logic-layer communication in 3-D ICs: Early design stage recommendations.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Abstracting Single Event Transient characteristics variations due to input patterns and fan-out.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.
J. Electron. Test., 2013
Soft error aware pipelined architecture: Leveraging automatic repeat request protocol.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Modified null convention logic pipeline to detect soft errors in both null and data phases.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
2011
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs.
Integr., 2011
SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2007
Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004