Mohammad Taherzadeh-Sani

According to our database1, Mohammad Taherzadeh-Sani authored at least 38 papers between 2003 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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On csauthors.net:

Bibliography

2020
A 17 Gbps 156 fJ/bit Two-Channel Optical Receiver With Optical-Input Split and Delay in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Low-Voltage High-Precision Time-Domain Winner-Take-All Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
An Analog LO Harmonic Suppression Technique for SDR Receivers.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Algebraic Approach to Fast Estimation of the Threshold Voltage of Junctionless Double Gate MOSFETs Using the Gram Schmidt Method.
CoRR, 2019

2018
A 0.8-4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Envelope-tracking common-drain CMOS power amplifier with a switching-only supply modulator for LTE applications.
Microelectron. J., 2018

2017
A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing.
IEEE Trans. Very Large Scale Integr. Syst., 2017

65 nm CMOS switching discontinuous-conduction mode buck converter with 330 ns start-up time for light-load power-cycled applications.
IET Circuits Devices Syst., 2017

A calibration-free 13-bit 0.9 V differential SAR-ADC with hybrid DAC and dithering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A 27 mV output ripple 92% efficiency buck converter using a multi-bit delta-sigma modulator controller and segmented output switch in 180 nm CMOS.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Single-ended impedance-modulation equalization for low-power differential voltage-mode drivers.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
A 350-MS/s Continuous-Time Delta-Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Low-energy CMOS common-drain power amplifier for short-range applications.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A 10-bit 110 kS/s 1.16 µW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
A Reconfigurable and Power-Scalable 10-12 Bit 0.4-44 MS/s Pipelined ADC With 0.35-0.5 pJ/Step in 1.2 V 90 nm Digital CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668].
IEEE J. Solid State Circuits, 2012

2011
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS.
IEEE J. Solid State Circuits, 2011

2010
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A reconfigurable 10-12b 0.4-44MS/s pipelined ADC with 0.35-0.5pJ/step in 1.2V 90nm digital CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2007
Power Optimization of Pipelined ADCs with High-Order Digital Gain Calibration.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Analysis of dynamic element matching (DEM) in pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Modeling of MOS transistors based on genetic algorithm and simulated annealing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power consumption issues in high-speed high-resolution pipelined A/D converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A pseudo-class-AB telescopic-cascode operational amplifier.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter].
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Systematic Design for Optimization of High-Resolution Pipelined ADCs.
Proceedings of the 2004 Design, 2004

2003
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications.
Integr., 2003

A low-power design methodology for high-resolution pipelined analog-to-digital converters.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A novel frequency compensation technique for two-stage CMOS operational amplifiers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25-μm CMOS.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003


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