Armin Tajalli

According to our database1, Armin Tajalli authored at least 66 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.
IEEE J. Solid State Circuits, 2020

Digitally-Assisted Peak Detector for Periodic Signal.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Power System Emulator Based on PLL Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2018
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects.
IEEE J. Solid State Circuits, 2016

A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces.
IEEE J. Solid State Circuits, 2015

A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces.
Int. J. Circuit Theory Appl., 2015

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2012
Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011
Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design trade-offs in ultra-low-power CMOS and STSCL digital systems.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits.
J. Low Power Electron., 2010

A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Leakage Current Reduction Using Subthreshold Source-Coupled Logic.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.
Microelectron. J., 2009

A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology.
IEEE J. Solid State Circuits, 2009

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications.
IEEE J. Solid State Circuits, 2008

Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance.
IET Circuits Devices Syst., 2008

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Improving the power-delay product in SCL circuits using source follower output stage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication.
IEEE J. Solid State Circuits, 2007

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits.
J. Low Power Electron., 2007

A Power Optimized Base-Band Circuitry for the Low-IF Receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 1/4 rate linear phase detector for PLL-based CDR circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A technique to suppress tail current flicker noise in CMOS LC VCOs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
A low-power, multichannel gated oscillator-based CDR for short-haul applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
Proceedings of the 2005 Design, 2005

A fractional delay-locked loop for on chip clock generation applications.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A duty cycle control circuit for high speed applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design and optimization of a high PSRR CMOS bandgap voltage reference.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Structured design of an integrated subscriber line interface system and circuit.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A compact biquadratic g/sub m/-C filter structure for low-voltage and high frequency applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A compact, low power, fully integrated clock frequency doubler.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
A low-power subscriber line interface circuit in a high-voltage CMOS technology.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
A 1.5-V supply, video range frequency, Gm-C filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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