Odile Liboiron-Ladouceur
Orcid: 0000-0001-6238-5346
According to our database1,
Odile Liboiron-Ladouceur
authored at least 48 papers
between 2003 and 2023.
Collaborative distances:
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Bibliography
2023
Improving Fabrication Fidelity of Integrated Nanophotonic Devices Using Deep Learning.
CoRR, 2023
Addressing the programming challenges of practical interferometric mesh based optical processors.
CoRR, 2023
Proceedings of the International Conference on Photonics in Switching and Computing, 2023
A Modified Mesh with Individually Monitored Interferometers for Fast Programmable Optical Processors.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
CMOS-Driven VCSEL-Based Photonic Links: an Exploration of the Power-Sensitivity Trade-Off.
IEEE Access, 2022
A Segmented Push-Pull MZI Coupled Silicon Ring Resonator for Spectral Efficient Modulation.
Proceedings of the 2022 27th OptoElectronics and Communications Conference (OECC) and 2022 International Conference on Photonics in Switching and Computing (PSC), 2022
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End.
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
High Radix SOA-Based Lossless Optical Switch Prototyping for 25 GBaud PAM4 Transmission in Modern Intra-datacenter Applications.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed-Solomon Codes for Short-Reach Optical Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 17 Gbps 156 fJ/bit Two-Channel Optical Receiver With Optical-Input Split and Delay in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A 12.5 Gb/s 1.93 pJ/Bit Optical Receiver Exploiting Silicon Photonic Delay Lines for Clock Phases Generation Replacement.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Survey of Optical and Electronic Delay Lines with a Case Study on Using Optical Delay Lines in 65 nm CMOS Optical Receivers.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019
Proceedings of the 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019
2018
1.23-pJ/bit 25-Gb/s Inductor-Less Optical Receiver With Low-Voltage Silicon Photodetector.
IEEE J. Solid State Circuits, 2018
DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
Co-design of a low-latency centralized controller for silicon photonic multistage MZI-based switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017
Demonstration of a packaged photonic integrated network on chip controlled by an FPGA-based scheduler.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017
Low-noise optical receiver front-end using narrow-bandwidth TIA and cascaded linear equalizer.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks.
IEEE Commun. Lett., 2016
Modelling and simulation of optical integrated networks for early-stage design exploration (WIP).
Proceedings of the Summer Computer Simulation Conference, 2016
Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Towards a fast centralized controller for integrated silicon photonic multistage MZI-based switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Ring versus bus topology: A network performance comparison of photonic integrated NoC.
Proceedings of the 18th International Conference on Transparent Optical Networks, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Fast scheduling based on iterative parallel wavelength matching for a multi-wavelength ring network-on-chip.
Proceedings of the 2015 International Conference on Optical Network Design and Modeling, 2015
Proceedings of the European Conference on Optical Communication, 2015
2014
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014
Proceedings of the European Conference on Networks and Communications, 2014
2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Power and noise configurable phase-locked loop using multi-oscillator feedback alignment.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of IEEE International Conference on Communications, 2012
2011
JOCN, 2011
A Scalable Space-Time Multi-plane Optical Interconnection Network Using Energy-Efficient Enabling Technologies [Invited].
JOCN, 2011
2007
Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network.
Proceedings of the 2007 IEEE International Test Conference, 2007
2003
Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003