Anas A. Hamoui

According to our database1, Anas A. Hamoui authored at least 29 papers between 2002 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Design and Verification of a Switchable Opamp for Switched-Capacitor Integrators.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A current-output DAC for low-power low-noise log-domain ΔΣ modulators.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013
A Reconfigurable and Power-Scalable 10-12 Bit 0.4-44 MS/s Pipelined ADC With 0.35-0.5 pJ/Step in 1.2 V 90 nm Digital CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 1-V 13-mW Single-Path Frequency-Translating ΔΣ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz.
IEEE J. Solid State Circuits, 2013

On the settling of nondelaying cascaded switched-capacitor integrators.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A current-mirror opamp with switchable transconductances for low-power switched-capacitor integrators.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668].
IEEE J. Solid State Circuits, 2012

A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a ΔΣ-Modulator Controller With a Scalable Sampling Frequency.
IEEE J. Solid State Circuits, 2012

2011
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS.
IEEE J. Solid State Circuits, 2011

A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Guest Editorial - Selected Papers From the 2010 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE Trans. Biomed. Circuits Syst., 2010

A reconfigurable 10-12b 0.4-44MS/s pipelined ADC with 0.35-0.5pJ/step in 1.2V 90nm digital CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Design Constraints for Image-Reject Frequency-Translating Delta Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Analysis of Clock-Jitter Effects in Continuous-Time Delta Sigma Modulators Using Discrete-Time Models.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Digitally-enhanced 2nd-order DeltaSigma modulator with unity-gain signal transfer function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Continuous-time DeltaSigma modulators with noise-transfer-function enhancement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An anti-aliasing filter inspired by continuous-time ΔΣ modulation.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Digitally-enhanced high-order ΔΣ modulators.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Polysilicon vertical actuator powered with waste heat.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Power Optimization of Pipelined ADCs with High-Order Digital Gain Calibration.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Analysis of dynamic element matching (DEM) in pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2002
Linearity enhancement of multibit Delta-Sigma modulators using pseudo data-weighted averaging.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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