Mohammadreza Soltaniyeh

Orcid: 0000-0002-2608-7322

According to our database1, Mohammadreza Soltaniyeh authored at least 8 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2022
An Accelerator for Sparse Convolutional Neural Networks Leveraging Systolic General Matrix-matrix Multiplication.
ACM Trans. Archit. Code Optim., 2022

Near-Storage Processing for Solid State Drive Based Recommendation Inference with SmartSSDs®.
Proceedings of the ICPE '22: ACM/SPEC International Conference on Performance Engineering, Bejing, China, April 9, 2022

2021
SPOTS: An Accelerator for Sparse CNNs Leveraging General Matrix-Matrix Multiplication.
CoRR, 2021

Near-Storage Acceleration of Database Query Processing with SmartSSDs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Synergistic CPU-FPGA Acceleration of Sparse Linear Algebra.
CoRR, 2020

2018
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2016
Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2013
Quota setting router architecture for quality of service in GALS NoC.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013


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