Ismail Kadayif

According to our database1, Ismail Kadayif authored at least 49 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2018
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

2016
Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Energy reduction in 3D NoCs through communication optimization.
Computing, 2015

2013
Hardware/software approaches for reducing the process variation impact on instruction fetches.
ACM Trans. Design Autom. Electr. Syst., 2013

2010
Modeling soft errors for data caches and alleviating their effects on data reliability.
Microprocess. Microsystems, 2010

2008
Capturing and optimizing the interactions between prefetching and cache line turnoff.
Microprocess. Microsystems, 2008

2007
Reducing Data TLB Power via Compiler-Directed Address Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Modeling and improving data cache reliability.
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

2006
Prefetching-aware cache line turnoff for saving leakage energy.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Optimizing Array-Intensive Applications for On-Chip Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 2005

Optimizing instruction TLB energy using software and hardware techniques.
ACM Trans. Design Autom. Electr. Syst., 2005

Compiler-directed high-level energy estimation and optimization.
ACM Trans. Embedded Comput. Syst., 2005

Data space-oriented tiling for enhancing locality.
ACM Trans. Embedded Comput. Syst., 2005

An integer linear programming-based tool for wireless sensor networks.
J. Parallel Distributed Comput., 2005

Compiling for memory emergency.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

Studying interactions between prefetching and cache line turnoff.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Compiler-directed scratch pad memory optimization for embedded multiprocessors.
IEEE Trans. VLSI Syst., 2004

Quasidynamic Layout Optimizations for Improving Data Locality.
IEEE Trans. Parallel Distrib. Syst., 2004

Access Pattern Restructuring for Memory Energy.
IEEE Trans. Parallel Distrib. Syst., 2004

A compiler-based approach for dynamically managing scratch-pad memories in embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Compiler-directed physical address generation for reducing dTLB power.
Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

Compiler-Guided Code Restructuring for Improving Instruction TLB Energy Behavior.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors.
Proceedings of the 2004 Design, 2004

Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks.
Proceedings of the 2004 Design, 2004

Compiler-directed code restructuring for reducing data TLB energy.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Managing Leakage Energy in Cache Hierarchies.
J. Instruction-Level Parallelism, 2003

An Energy-Oriented Evaluation of Communication Optimizations for Microcensor Networks.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Compiler-Directed Management of Instruction Accesses.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

An Integrated Approach for Improving Cache Behavior.
Proceedings of the 2003 Design, 2003

Generalized Data Transformations for Enhancing Cache Behavior.
Proceedings of the 2003 Design, 2003

Hardware/Software Techniques for Improving Cache Performance in Embedded Systems.
Proceedings of the Embedded Software for SoC, 2003

Generalized Data Transformations.
Proceedings of the Embedded Software for SoC, 2003

2002
Generating physical addresses directly for saving instruction TLB energy.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A Hybrid Strategy Based on Data Distribution and Migration for Optimizing Memory Locality.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

EAC: A Compiler Framework for High-Level Energy Estimation and Optimization.
Proceedings of the 2002 Design, 2002

An integer linear programming based approach for parallelizing applications in On-chip multiprocessors.
Proceedings of the 39th Design Automation Conference, 2002

An energy saving strategy based on adaptive loop parallelization.
Proceedings of the 39th Design Automation Conference, 2002

Locality-conscious process scheduling in embedded systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Influence of Loop Optimizations on Energy Consumption of Multi-bank Memory Systems.
Proceedings of the Compiler Construction, 11th International Conference, 2002

Optimizing inter-nest data locality.
Proceedings of the International Conference on Compilers, 2002

Leakage Energy Management in Cache Hierarchies.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
vEC: virtual energy counters.
Proceedings of the 2001 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis For Software Tools and Engineering, 2001

Morphable Cache Architectures: Potential Benefits.
Proceedings of The Workshop on Languages, 2001

Exploiting scratch-pad memory using Presburger formulas.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Dynamic Management of Scratch-Pad Memory Space.
Proceedings of the 38th Design Automation Conference, 2001

Compiler-directed selection of dynamic memory layouts.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001


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