Siamak Mohammadi

Orcid: 0000-0003-1515-7281

According to our database1, Siamak Mohammadi authored at least 78 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Model Checking of Hyperledger Fabric Smart Contracts.
Proceedings of the 28th IEEE International Conference on Emerging Technologies and Factory Automation, 2023

2022
A power constrained approximate multiplier with a high level of configurability.
Microprocess. Microsystems, April, 2022

MAGNETIC: Multi-Agent Machine Learning-Based Approach for Energy Efficient Dynamic Consolidation in Data Centers.
IEEE Trans. Serv. Comput., 2022

Infrastructure Aware Heterogeneous-Workloads Scheduling for Data Center Energy Cost Minimization.
IEEE Trans. Cloud Comput., 2022

High-level Modeling and Verification Platform for Elastic Circuits with Process Variation Considerations.
ACM J. Emerg. Technol. Comput. Syst., 2022

2021
THAMON: Thermal-aware High-performance Application Mapping onto Opto-electrical network-on-chip.
J. Syst. Archit., 2021

2020
Prediction-based underutilized and destination host selection approaches for energy-efficient dynamic VM consolidation in data centers.
J. Supercomput., 2020

Power loss analysis in thermally-tuned nanophotonic switch for on-chip interconnect.
Nano Commun. Networks, 2020

Vulnerability assessment of fault-tolerant optical network-on-chips.
J. Parallel Distributed Comput., 2020

Process variation-aware approximate full adders for imprecision-tolerant applications.
Comput. Electr. Eng., 2020

Insertion loss-aware application mapping onto the optical Cube-Connected Cycles architecture.
Comput. Electr. Eng., 2020

Developing Safe Smart Contracts.
Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020

2019
CMV: Clustered Majority Voting Reliability-Aware Task Scheduling for Multicore Real-Time Systems.
IEEE Trans. Reliab., 2019

SORT: Semi Online Reliable Task Mapping for Embedded Multi-Core Systems.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2019

Fault tolerant non-linear techniques for scalar multiplication in ECC.
Proceedings of the 16th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology, 2019

2018
Hypervisor and Neighbors' Noise: Performance Degradation in Virtualized Environments.
IEEE Trans. Serv. Comput., 2018

A Majority-Based Reliability-Aware Task Mapping in High-Performance Homogenous NoC Architectures.
ACM Trans. Embed. Comput. Syst., 2018

A high performance dual clock elastic FIFO network interface for GALS NoC.
Microelectron. J., 2018

Energy efficient configuration unification and compression for CGRAs.
Microprocess. Microsystems, 2018

Elastic buffer evaluation for link pipelining under process variation.
IET Circuits Devices Syst., 2018

LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

Exploration of approximate multipliers design space using carry propagation free compressors.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
A self-organized load balancing mechanism for cloud computing.
Concurr. Comput. Pract. Exp., 2017

Cache Energy Management through Dynamic Reconfiguration Approach in Opto-Electrical NoC.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications.
Proceedings of the Euromicro Conference on Digital System Design, 2017

CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Statistical analysis of asynchronous pipelines in presence of process variation using formal models.
Integr., 2016

Application-aware Retiming of Accelerators: A High-level Data-driven Approach.
CoRR, 2016

Clustering Effects on the Design of Opto-Electrical Network-on-Chip.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

2015
Gem5v: a modified gem5 for simulating virtualized systems.
J. Supercomput., 2015

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators.
IEEE Trans. Computers, 2015

Variation-aware approaches with power improvement in digital circuits.
Integr., 2015

Distributed consolidation of virtual machines for power efficiency in heterogeneous cloud data centers.
Comput. Electr. Eng., 2015

A Clustered GALS NoC Architecture with Communication-Aware Mapping.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014
High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET Technology.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Distributed fair DRAM scheduling in network-on-chips architecture.
J. Syst. Archit., 2013

Functional and Performance Analysis of Network-on-Chips Using Actor-based Modeling and Formal Verification.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2013

Quota setting router architecture for quality of service in GALS NoC.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Modeling symmetrical independent gate FinFET using predictive technology model.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Adaptive Input-Output Selection Based On-Chip Router Architecture.
J. Low Power Electron., 2012

A tightly-coupled multi-core cluster with shared-memory HW accelerators.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Power-aware game for cloud computing: A distributed mechanism based on Game Theory for minmizing power consumption in cloud scale datacenter.
Proceedings of the 6th International Symposium on Telecommunications, 2012

A synthesis algorithm for customized heterogeneous multi-processors.
Proceedings of the International SoC Design Conference, 2012

2011
Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling.
Microelectron. J., 2011

Designing robust threshold gates against soft errors.
Microelectron. J., 2011

Modified bundled-data as a new protocol for NoC asynchronous links.
Microelectron. J., 2011

On the Potentials of FinFETs for Asynchronous Circuit Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Designing Robust Asynchronous Circuits Based on FinFET Technology.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

An adaptive fuzzy logic-based routing algorithm for networks-on-chip.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
A dual mode UHF EPC Gen 2 RFID tag in 0.18 µm CMOS.
Microelectron. J., 2010

Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling.
IET Comput. Digit. Tech., 2010

A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A High Throughput Low Power FIFO Used for GALS NoC Buffers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Low-distance path-based multicast routing algorithm for network-on-chips.
IET Comput. Digit. Tech., 2009

A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Graph based test case generation for TLM functional verification.
Microprocess. Microsystems, 2008

Inherent reliability evaluation of Networks-on-Chip based on analytical models.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A novel test environment for template based QDI asynchronous circuits.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A dual mode EPC Gen 2 UHF RFID transponder in 0.18μm CMOS.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

PAMPR: Power-aware and minimum path routing algorithm for NoCs.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Optimized Assignment Coverage Computation in Formal Verification of Digital Systems.
Proceedings of the 16th Asian Test Symposium, 2007

System Level Voltage Scheduling Technique Using UML-RT Model.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

A Superior Low Complexity Rate Control Algorithm.
Proceedings of the 2007 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2007), 2007

2006
Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
Proceedings of the International Symposium on System-on-Chip, 2006

2000
AMULET3i - An Asynchronous System-on-Chip.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1994
A New Massively Parallel Architecture Relying On Asynchronous Communications.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

A new scheme for massively parallel image analysis.
Proceedings of the 12th IAPR International Conference on Pattern Recognition, 1994


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