Virginie Fresse

Orcid: 0000-0002-9944-0174

According to our database1, Virginie Fresse authored at least 47 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Federated learning compression designed for lightweight communications.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2021
Accelerating DNNs from local to virtualized FPGA in the Cloud: A survey of trends.
J. Syst. Archit., 2021

An approach for an efficient sharing of IP as a Service in cloud FPGA.
Proceedings of the 18th International Multi-Conference on Systems, Signals & Devices, 2021

2020
A Multi-Edge-Agent System approach for sharing heterogeneous computing resources.
Proceedings of the 92nd IEEE Vehicular Technology Conference, 2020

Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing cluster.
Proceedings of the International Workshop on Rapid System Prototyping, 2020

Pooling of Heterogeneous Computing Resources: A Novel Approach based on Multi-Edge-Agent Concept.
Proceedings of the 12th International Conference on Agents and Artificial Intelligence, 2020

2019
From FPGA to Support Cloud to Cloud of FPGA: State of the Art.
Int. J. Reconfigurable Comput., 2019

Improving Video Object Detection by Seq-Bbox Matching.
Proceedings of the 14th International Joint Conference on Computer Vision, 2019

2017
A collision management structure for NoC deployment on multi-FPGA.
Microprocess. Microsystems, 2017

Proposition and evaluation of a real-time generic architecture for a laser stripe detection system on FPGA.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Challenges of virtualization FPGA in a cloud context.
Proceedings of the IEEE International Conference on Computational Intelligence and Virtual Environments for Measurement Systems and Applications, 2017

2016
Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chip.
J. Supercomput., 2016

Synthesis of dependency-aware traffic generators from NoC simulation traces.
J. Syst. Archit., 2016

A survey of NoC evaluation platforms on FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

FPGA memory optimization for real-time imaging.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Task mapping and mesh topology exploration for an FPGA-based network on chip.
Microprocess. Microsystems, 2015

Dynamic data flow analysis for NoC based application synthesis.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Differentiated service for NoC-based multimedia applications.
Proceedings of the 27th International Conference on Microelectronics, 2015

Methodological Framework for NoC Resources Dimensioning on FPGAs.
Proceedings of the 10th International Conference on Future Networks and Communications (FNC 2015) / The 12th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2015) / Affiliated Workshops, 2015

2014
Evaluation of SNMP-like protocol to manage a NoC emulation platform.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Mathematical Models Applied to On-Chip Network on FPGA for Resource Estimation.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

A Novel Architecture for Inter-FPGA Traffic Collision Management.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

2013
FlexOE: A congestion-aware routing algorithm for NoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Adaptive NoC-based MPSoC system for spectral imaging algorithm dedicated to art authentication.
Proceedings of the 21st European Signal Processing Conference, 2013

2012
Case study: Deployment of the 2D NoC on 3D for the generation of large emulation platforms.
Proceedings of the 3rd International Conference on Image Processing Theory Tools and Applications, 2012

2011
Generation of emulation platforms for NoC exploration on FPGA.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Evaluation of CPU and GPU architectures for spectral image analysis algorithms.
Proceedings of the Conference on Parallel Processing for Imaging Applications 2011, 2011

From mono-FPGA to multi-FPGA emulation platform for NoC performance evaluations.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

2010
Exploration of an adaptive NoC architecture on FPGA dedicated to multi and hysperspectral algorithm for art authentication.
Proceedings of the 2nd International Conference on Image Processing Theory Tools and Applications, 2010

GPU architecture evaluation for multispectral and hyperspectral image analysis.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications.
EURASIP J. Embed. Syst., 2009

GALS NoC architectures on FPGA dedicated to multispectral image applications.
Proceedings of the 17th European Signal Processing Conference, 2009

2008
A Case Study: Quantitative Evaluation of C-Based High-Level Synthesis Systems.
EURASIP J. Embed. Syst., 2008

An adaptive embedded architecture for real-time Particle Image Velocimetry algorithms
CoRR, 2008

A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Adaptive FPGA NoC-based Architecture for Multispectral Image Correlation.
Proceedings of the 4th European Conference on Colour in Graphics, 2008

2007
A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis.
EURASIP J. Embed. Syst., 2007

Rapid prototyping of image analysis algorithms on an adaptive FGPA architecture.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
System on chip FPGA designs of a parameterized particle image velocimetry algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An adaptive and predictive architecture for parameterised PIV algorithms.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Anadaptive embedded architecture for real-time Particle Image Velocimetry algorithms.
Proceedings of the 14th European Signal Processing Conference, 2006

2002
ARIAL: Rapid Prototyping for Mixed and Parallel Platforms.
Parallel Comput., 2002

AVSynDEx: A Rapid Prototyping Process Dedicated to the Implementation of Digital Image Processing Applications on Multi-DSP and FPGA Architectures.
EURASIP J. Adv. Signal Process., 2002

A VsynDEx Methodology for Fast Prototyping of Multi-C6x DSP Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

A high-level development tool dedicated to the generation of cores for the implementation of image processing applications.
Proceedings of the 11th European Signal Processing Conference, 2002

2000
Prototyping for parallel and mixed architectures. Implementation of a new image compression method: LAR.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Rapid prototyping for mixed architectures.
Proceedings of the IEEE International Conference on Acoustics, 2000


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