Dominique Houzet

According to our database1, Dominique Houzet authored at least 60 papers between 1991 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
3D Dense & Scaled Reconstruction Pipeline with Smartphone Acquisition.
Proceedings of the Intelligent Systems and Pattern Recognition, 2022

2020
Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU-GPU platforms.
J. Real Time Image Process., 2020

Online GPUAnalysis using Adaptive DMA Controlled by Softcore for 2D Detectors.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018
Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection.
Proceedings of the 5th IEEE International Congress on Information Science and Technology, 2018

Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection.
Proceedings of the 4th International Conference on Advanced Technologies for Signal and Image Processing, 2018

2016
Contribution of color in saliency model for videos.
Signal Image Video Process., 2016

A domain-specific high-level programming model.
Concurr. Comput. Pract. Exp., 2016

Special session 1 automotive parallel computing challenges - architectures, applications and tricks.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

FPGA memory optimization for real-time imaging.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2014
Efficient implementation of data flow graphs on multi-gpu clusters.
J. Real Time Image Process., 2014

Contribution of Color Information in Visual Saliency Model for Videos.
Proceedings of the Image and Signal Processing - 6th International Conference, 2014

SignalPU: A Programming Model for DSP Applications on Parallel and Heterogeneous Clusters.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Color information in a model of saliency.
Proceedings of the 22nd European Signal Processing Conference, 2014

A Visual Programming Model to Implement Coarse-Grained DSP Applications on Parallel and Heterogeneous Clusters.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2013
Improving Visual Saliency by Adding 'Face Feature Map' and 'Center Bias'.
Cogn. Comput., 2013

Impact of 3D IC on NoC Topologies: A Wire Delay Consideration.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Tetrahedral volume reconstruction in X-ray tomography using GPU architecture.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

A 3D reconstruction from real-time stereoscopic images using GPU.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Face perception: Influence of location and number in videos.
Proceedings of the 13th International Workshop on Image Analysis for Multimedia Interactive Services, 2012

Investigating performance variations of an optimized GPU-ported granulometry algorithm.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Parallel implementation of a spatio-temporal visual saliency model.
J. Real Time Image Process., 2011

Evaluation of CPU and GPU architectures for spectral image analysis algorithms.
Proceedings of the Conference on Parallel Processing for Imaging Applications 2011, 2011

Spatio-temporal fusion of visual attention model.
Proceedings of the 19th European Signal Processing Conference, 2011

3D multiprocessor with 3D NoC architecture based on Tezzaron technology.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Effficient stackless ray traversal for bounding sphere hierarchies with CUDA.
Proceedings of the International Conference on Computational Science, 2010

SysCellC: a data-flow programming model on multi-GPU.
Proceedings of the International Conference on Computational Science, 2010

A Programming Model and a NoC-Based Architecture for Streaming Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

GPU implementation of motion estimation for visual saliency.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

GPU architecture evaluation for multispectral and hyperspectral image analysis.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications.
EURASIP J. Embed. Syst., 2009

Another take on functional system-level design and modeling.
Proceedings of the Forum on specification and Design Languages, 2009

2008
A Case Study: Quantitative Evaluation of C-Based High-Level Synthesis Systems.
EURASIP J. Embed. Syst., 2008

High Speed 3D Tomography on CPU, GPU, and FPGA.
EURASIP J. Embed. Syst., 2008

A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs.
EURASIP J. Embed. Syst., 2008

Hardware Simulator for MIMO Radio Channels: Design and Features of the Digital Block.
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008

A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

SysCellC: SystemC on Cell.
Proceedings of the Selected Papers of the Sixth International Conference on Computational Sciences and Its Applications, 2008

2006
Generation of Embedded Hardware/Software from SystemC.
EURASIP J. Embed. Syst., 2006

NoC Design Flow for TDMA and QoS Management in a GALS Context.
EURASIP J. Embed. Syst., 2006

Automated derivation of NoC Communication Specifications from Application Constraints.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Design of the Digital Block of a Hardware Simulator for MIMO Radio Channels.
Proceedings of the IEEE 17th International Symposium on Personal, 2006

A high level SoC power estimation based on IP modeling.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Object Recognition System-on-Chip Using the Support Vector Machines.
EURASIP J. Adv. Signal Process., 2005

Proposition of a benchmark for evaluation of cores mapping onto NoC architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Systematic Figure of Merit Computation for the Design of Pipeline ADC.
Proceedings of the 2005 Design, 2005

2004
Easy SoC Design with VCI SystemC Adapters.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2002
VSIA Interface Cosynthesis.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2000
Implementation of the SVM Neural Network Generalization Function for Image Processing.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000

1999
A shared memory model on a cluster of PCs.
Microprocess. Microsystems, 1999

Computer architecture development courses in Toulouse Universities.
Proceedings of the 1999 workshop on Computer architecture education, 1999

High Level Communication Constructs for Distributed Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

A Shared Memory Model on a Cluster of PCs.
Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

1998
Pc-based Shared Memory Architecture and Language.
J. Supercomput., 1998

1996
Real-Time Image Processing with a MIMD Computer.
Real Time Imaging, 1996

1993
A 1D linearly expandable interconnection network performance analysis.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
Performance Analysis of the Network of the GFLOPS Parallel Architecture.
Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992

1991
GFLOPS: a general flexible linearly organized parallel structure for images.
Proceedings of the Application Specific Array Processors, 1991


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