Mohammed Zackriya V

According to our database, Mohammed Zackriya V authored at least 9 papers between 2013 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Top-down Physical Design of Soft Embedded FPGA Fabrics.

Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes.

Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi

IEEE Trans. Very Large Scale Integr. Syst., 2020

Latch-Based Logic Locking.

Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2017

Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line.

Mohammed Zackriya V, Harish M. Kittur

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Precharge-Free, Low-Power Content-Addressable Memory.

V. Mohammed Zackriya, Harish M. Kittur

IEEE Trans. Very Large Scale Integr. Syst., 2016

Low Energy Metric Content Addressable Memory (CAM) with Multi Voltage Matchline Segments.

V. Mohammed Zackriya, Harish M. Kittur

J. Circuits Syst. Comput., 2016

2014

Low Power fractional-n frequency Divider with Improved Resolution.

V. Mohammed Zackriya, John Reuben, Ashim Harsh, Harish M. Kittur

J. Circuits Syst. Comput., 2014

Selective Match-Line Energizer Content Addressable Memory(SMLE -CAM).

V. Mohammed Zackriya, Harish M. Kittur

CoRR, 2014

2013

Capacitance driven clock mesh synthesis to minimize skew and power dissipation.

John Reuben, V. Mohammed Zackriya, Salma Nashit, Harish M. Kittur

IEICE Electron. Express, 2013