Joseph Sweeney

Orcid: 0000-0002-3775-8638

According to our database1, Joseph Sweeney authored at least 12 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1994, "For fostering research and development activities across several disciplines".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Quantifying the Efficacy of Logic Locking Methods.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2021
Obfuscation and Security for Digital Integrated Circuits.
PhD thesis, 2021

Split-Chip Design to Prevent IP Reverse Engineering.
IEEE Des. Test, 2021

Microfluidic-based Bacterial Molecular Computing on a Chip.
CoRR, 2021

Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A Method to Account for Personnel Risk Attitudes in System Design and Maintenance Activity Development.
Syst., 2020

CircuitGraph: A Python package for Boolean circuits.
J. Open Source Softw., 2020

Securing Digital Systems via Split-Chip Obfuscation.
CoRR, 2020

Sensitivity Analysis of Locked Circuits.
Proceedings of the LPAR 2020: 23rd International Conference on Logic for Programming, 2020

Modeling Techniques for Logic Locking.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Latch-Based Logic Locking.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2017
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017


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