Samuel Nascimento Pagliarini

CoRR, 2024

CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks.

[BibT_eX]

[DOI]

Levent Aksoy

Muhammad Yasin

CoRR, 2024

Utilizing Layout Effects for Analog Logic Locking.

[BibT_eX]

[DOI]

CoRR, 2024

2023

High-speed SABER key encapsulation mechanism in 65nm CMOS.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., November, 2023

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

A Versatile and Flexible Multiplier Generator for Large Integer Polynomials.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., September, 2023

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

Hybrid Protection of Digital FIR Filters.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., June, 2023

KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Towards High-speed ASIC Implementations of Post-Quantum Cryptography.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking.

[BibT_eX]

[DOI]

Levent Aksoy

Muhammad Yasin

CoRR, 2023

Multiplierless Design of High-Speed Very Large Constant Multiplications.

[BibT_eX]

[DOI]

CoRR, 2023

Impact of Orientation on the Bias of SRAM-Based PUFs.

[BibT_eX]

[DOI]

CoRR, 2023

SALSy: Security-Aware Layout Synthesis.

[BibT_eX]

[DOI]

Mohammad Eslami

CoRR, 2023

An Overview of FPGA-inspired Obfuscation Techniques.

[BibT_eX]

[DOI]

CoRR, 2023

Resynthesis-based Attacks Against Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

Multiplierless Design of Very Large Constant Multiplications in Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

KaLi: A Crystal for Post-Quantum Security.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs.

[BibT_eX]

[DOI]

CoRR, 2022

Preventing Distillation-based Attacks on Neural Network IP.

[BibT_eX]

[DOI]

CoRR, 2022

Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study.

[BibT_eX]

[DOI]

IEEE Access, 2022

Obfuscating the Hierarchy of a Digital IP.

[BibT_eX]

[DOI]

Giorgi Basiashvili

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks.

[BibT_eX]

[DOI]

Mahdieh Grailoo

Mairo Leier

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Mohammad Eslami

Tara Ghasempouri

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Hardware Obfuscation of Digital FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Leveraging Layout-based Effects for Locking Analog ICs.

[BibT_eX]

[DOI]

Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022

A Side-Channel Hardware Trojan in 65nm CMOS with $2\mu\mathrm{W}$ precision and Multi-bit Leakage Capability.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Design Space Exploration of SABER in 65nm ASIC.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Split-Chip Design to Prevent IP Reverse Engineering.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Hardware Trojan Insertion in Finalized Layouts: a Silicon Demonstration.

[BibT_eX]

[DOI]

CoRR, 2021

A Tutorial on Design Obfuscation: from Transistors to Systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-level Intellectual Property Obfuscation via Decoy Constants.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

An Open-source Library of Large Integer Polynomial Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Side-Channel Attacks on Triple Modular Redundancy Schemes.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

From FPGAs to Obfuscated eASICs: Design and Security Trade-offs.

[BibT_eX]

[DOI]

Tiago Diadami Perez

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2020

From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An Area Aware Accelerator for Elliptic Curve Point Multiplication.

[BibT_eX]

[DOI]

Muhammad Rashid

IACR Cryptol. ePrint Arch., 2020

A Systematic Study of Lattice-based NIST PQC Algorithms: from Reference Implementations to Hardware Accelerators.

[BibT_eX]

[DOI]

CoRR, 2020

Securing Digital Systems via Split-Chip Obfuscation.

[BibT_eX]

[DOI]

Joseph Sweeney

Lawrence T. Pileggi

CoRR, 2020

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges.

[BibT_eX]

[DOI]

IEEE Access, 2020

Latch-Based Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Design Obfuscation versus Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Latest Trends in Hardware Security and Privacy.

[BibT_eX]

[DOI]

Abderrahmane Sensaoui

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2019

2018

Application and Product-Volume-Specific Customization of BEOL Metal Pitch.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS.

[BibT_eX]

[DOI]

Thomas C. Jackson

Lawrence T. Pileggi

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

2017

Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits.

[BibT_eX]

[DOI]

Mohamad Imran Bin Bandan

Jimson Mathew

Dhiraj K. Pradhan

IEEE Trans. Reliab., 2017

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.

[BibT_eX]

[DOI]

Rajat Subhra Chakraborty

Jimson Mathew

Sree Ranjani Rajendran

M. Nirmala Devi

IEEE Trans. Emerg. Top. Comput., 2017

A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Virtual characterization for exhaustive DFM evaluation of logic cell libraries.

[BibT_eX]

[DOI]

Mayler G. A. Martins

Lawrence T. Pileggi

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2014

Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2014

A placement strategy for reducing the effects of multiple faults in digital circuits.

[BibT_eX]

[DOI]

Dhiraj K. Pradhan

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A hybrid reliability assessment method and its support of sequential logic modelling.

[BibT_eX]

[DOI]

Georgi Nedeltchev Gaydadjiev

Dhiraj K. Pradhan

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs.

[BibT_eX]

[DOI]

Ioannis Sourdis

Christos Strydis

Antonino Armato

Christos-Savvas Bouganis

Babak Falsafi

Dionisios N. Pnevmatikatos

Dimitris Theodoropoulos

Stavros Tzilis

Michalis Vavouras

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

SNaP: A novel hybrid method for circuit reliability assessment under multiple faults.

[BibT_eX]

[DOI]

Arwa Ben Dhia

Microelectron. Reliab., 2013

A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Arwa Ben Dhia

Habib Mehrez

Philippe Matherat

Microelectron. Reliab., 2013

Selective hardening against multiple faults employing a net-based reliability analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis.

[BibT_eX]

[DOI]

Tian Ban

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Single event transient mitigation through pulse quenching: Effectiveness at circuit level.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

Exploring the feasibility of selective hardening for combinational logic.

[BibT_eX]

[DOI]

G. G. dos Santos

Microelectron. Reliab., 2012

Selective hardening methodology for combinational logic.

[BibT_eX]

[DOI]

Proceedings of the 13th Latin American Test Workshop, 2012

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach.

[BibT_eX]

[DOI]

Arwa Ben Dhia

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

VEasy: a tool suite towards the functional verification challenges.

[BibT_eX]

[DOI]

PhD thesis, 2011

Exploring the Limitations of Software-based Techniques in SEE Fault Coverage.

[BibT_eX]

[DOI]

Lucas Rosa

J. Electron. Test., 2011

Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique.

[BibT_eX]

[DOI]

Maurício Altieri

Michael Hübner

Jürgen Becker

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

VEasy: A tool suite for teaching VLSI functional verification.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Evaluating coverage collection using the VEasy functional verification tool suite.

[BibT_eX]

[DOI]

Paulo André Haacke