Ken Mai

According to our database1, Ken Mai authored at least 58 papers between 1999 and 2018.

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2018
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming.
CoRR, 2018

Read Disturb Errors in MLC NAND Flash Memory.
CoRR, 2018

Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory.
CoRR, 2018

A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A compact energy-efficient pseudo-static camouflaged logic family.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Secure chip odometers using intentional controlled aging.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks.
IEEE Micro, 2016

Scalable High-Radix Modular Crossbar Switches.
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016

A secure camouflaged threshold voltage defined logic family.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

2015
Guest Editorial Special Section on Hardware Security and Trust.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement.
IACR Cryptology ePrint Archive, 2015

Deeply hardware-entangled reconfigurable logic and interconnect.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Modeling and Design of High-Radix On-Chip Crossbar Switches.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

High-efficiency crossbar switches using capacitively coupled signaling.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Statistical Learning in Chip (SLIC).
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

A DPA-resistant self-timed three-phase dual-rail pre-charge logic family.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Neighbor-cell assisted error correction for MLC NAND flash memories.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

SLIC: Statistical learning in chip.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states.
Proceedings of the 2013 IEEE International Test Conference, 2013

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling.
Proceedings of the Design, Automation and Test in Europe, 2013

A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2013, 2013

2012
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
CoRAM: an in-fabric memory architecture for FPGA-based computing.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

FPGA-Based Solid-State Drive Prototyping Platform.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010
Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems.
Proceedings of the IEEE, 2010

Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Side-channel Attack Resistant ROM-based AES S-Box.
Proceedings of the HOST 2010, 2010

A Comparison of Power-analysis-resistant Digital Circuits.
Proceedings of the HOST 2010, 2010

Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses.
Proceedings of the HOST 2010, 2010

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
Proceedings of the 47th Design Automation Conference, 2010

2009
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.
TRETS, 2009

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
Proceedings of the 27th International Conference on Computer Design, 2009

Low-overhead, digital offset compensated, SRAM sense amplifiers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
Proceedings of the IEEE, 2008

A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Mismatch analysis and statistical design at 65 nm and below.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2000
Smart Memories: a modular reconfigurable architecture.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

1999
Interconnect scaling implications for CAD.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999


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