Mohsen Naderi

According to our database1, Mohsen Naderi authored at least 6 papers between 2003 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Asynchronous vs. Synchronous Design of RSA.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

2004
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
An Asynchronous Viterbi Decoder for Low-Power Applications.
Proceedings of the Integrated Circuit and System Design, 2003


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