Mehdi Sedighi
Orcid: 0000-0002-8304-1304
According to our database1,
Mehdi Sedighi
authored at least 50 papers
between 2005 and 2023.
Collaborative distances:
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Bibliography
2023
Quantum Inf. Process., January, 2023
2022
IEEE Trans. Computers, 2022
2021
2020
IEEE Trans. Reliab., 2020
Comput. Biol. Chem., 2020
2018
Biosyst., 2018
2017
Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics.
ACM J. Emerg. Technol. Comput. Syst., 2017
CoRR, 2017
An optimized reconfigurable architecture for hardware implementation of decimal arithmetic.
Comput. Electr. Eng., 2017
2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Location-based scheduling: An approach to address challenges of Big Data and Mobile Cloud Computing.
Proceedings of the 8th International Symposium on Telecommunications, 2016
2015
Genet. Program. Evolvable Mach., 2015
A heuristic algorithm for high level synthesis of decimal arithmetic circuits using SystemC.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
2014
Quantum Inf. Process., 2014
Automatic translation of quantum circuits to optimized one-way quantum computation patterns.
Quantum Inf. Process., 2014
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates.
ACM J. Emerg. Technol. Comput. Syst., 2014
2013
Quantum Inf. Process., 2013
2012
A fast response dynamic bandwidth allocation algorithm for a converged EPON and WiMAX network.
Proceedings of the 6th International Symposium on Telecommunications, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Quantum Inf. Process., 2011
J. Signal Inf. Process., 2011
2010
Microelectron. J., 2010
ACM J. Emerg. Technol. Comput. Syst., 2010
2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEICE Electron. Express, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems.
Microprocess. Microsystems, 2006
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
A New Algorithm for Resource Manager to Enhance the Quality of Service in VoIP Systems.
Proceedings of the Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 2006
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005