Mostafa Khamis

Orcid: 0000-0002-4925-0575

According to our database1, Mostafa Khamis authored at least 14 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Emulation and verification framework for MPSoC based on NoC and RISC-V.
Des. Autom. Embed. Syst., December, 2022

2020
On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018
RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation.
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

A 4-PAM interconnect in network-on-chip for high-throughput and latency-sensitive applications.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017
A novel power reduction technique using wire multiplexing.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

F1A: Networks on chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Work-in-Progress: A Flexible Router Architecture for 3D NoCs.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

On Error Injection for NoC Platforms: A UVM-based Practical Case Study.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017

Performance evaluation of virtual channel flow control in centralized and distributed networks for system on chip.
Proceedings of the 29th International Conference on Microelectronics, 2017

A novel assertions-based code coverage automatic CAD tool.
Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017

A reusable verification environment for NoC platforms using UVM.
Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017

2016
A narrative of UVM testbench environment for interconnection routers: A practical approach.
Proceedings of the 11th International Design & Test Symposium, 2016

2015
Evaluating the feasibility of centralized router for network on chip.
Proceedings of the 27th International Conference on Microelectronics, 2015


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