Mahmoud A. Elmohr

According to our database, Mahmoud A. Elmohr authored at least 8 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

TurboHE: Accelerating Fully Homomorphic Encryption Using FPGA Clusters.

Haohao Liao, Mahmoud A. Elmohr, Xuan Dong, Yanjun Qian, Wenzhe Yang, Zhiwei Shang, Yin Tan

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

2020

EM Fault Injection on ARM and RISC-V.

Mahmoud A. Elmohr, Haohao Liao, Catherine H. Gebotys

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Going Deep: Using deep learning techniques with simplified mathematical models against XOR BR and TBR PUFs (Attacks and Countermeasures).

Mahmoud Khalafalla, Mahmoud A. Elmohr, Catherine H. Gebotys

Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2018

RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC.

Mahmoud A. Elmohr, Ahmed S. Eissa, Moamen Ibrahim, Mostafa Khamis, Sameh El-Ashry, Ahmed Shalaby, Mohamed Abdelsalam, M. Watheq El-Kharashi

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption.

Mahmoud A. Elmohr, Sachin Kumar, Mustafa Khairallah, Anupam Chattopadhyay

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

A reusable verification environment for NoC platforms using UVM.

Ahmed S. Eissa, Moamen A. Ibrahem, Mahmoud A. Elmohr, Yasmin Zamzam, Ahmed El-Yamany, Sameh El-Ashry, Mostafa Khamis, Ahmed Shalaby

Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017

2016

Hardware implementation of a SHA-3 application-specific instruction set processor.

Mahmoud A. Elmohr, Mostafa A. Saleh, Ahmed S. Eissa, Khaled E. Ahmed, Mohammed M. Farag

Proceedings of the 28th International Conference on Microelectronics, 2016

SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture.

Ahmed S. Eissa, Mahmoud A. Elmohr, Mostafa A. Saleh, Khaled E. Ahmed, Mohammed M. Farag

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016