N. Prasad

According to our database, N. Prasad authored at least 12 papers between 2014 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Embedding delay-based physical unclonable functions in networks-on-chip.

Prasad Nagabhushanamgari, Vikash Sehwag, Indrajit Chakrabarti, Santanu Chattopadhyay

IET Circuits Devices Syst., 2021

2019

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip.

N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti

CoRR, 2019

2018

A Parallel Stochastic Number Generator With Bit Permutation Networks.

Vikash Sehwag, N. Prasad, Indrajit Chakrabarti

IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture.

N. Prasad, Indrajit Chakrabarti, Santanu Chattopadhyay

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Design and evaluation of ZMesh topology for on-chip interconnection networks.

N. Prasad, Priyajit Mukherjee, Santanu Chattopadhyay, Indrajit Chakrabarti

J. Parallel Distributed Comput., 2018

2017

A New Logic Encryption Strategy Ensuring Key Interdependency.

Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Runtime mitigation of illegal packet request attacks in Networks-on-Chip.

N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Approximate conditional carry adder for error tolerant applications.

Avishek Sinha Roy, N. Prasad, Anindya Sundar Dhar

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip.

N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti

Microprocess. Microsystems, 2015

Multiplier-less VLSI architectures for radix-2² folded pipelined complex FFT core.

Abhishek Mankar, N. Prasad, Ansuman DiptiSankar Das, Sukadev Meher

Int. J. Circuit Theory Appl., 2015

ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms.

N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

A spare link based reliable Network-on-Chip design.

Navonil Chatterjee, N. Prasad, Santanu Chattopadhyay

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014