Nak-Woong Eum

According to our database1, Nak-Woong Eum authored at least 23 papers between 2001 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2016
Reduced complexity single core based HEVC video codec processor for mobile 4K-UHD applications.
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016

2015
A hybrid embedded compression codec engine for ultra HD video application.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Virtual prototype based on Aldebarn CPU core.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

2014
Multi-core based HEVC hardware decoding system.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2014

2012
Multi-core architecture for video decoding.
Proceedings of the International SoC Design Conference, 2012

2011
Application specific processor for multi-standard video decoding.
Proceedings of the International SoC Design Conference, 2011

A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder.
Proceedings of the International SoC Design Conference, 2011

Development of portable sound effector.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011

2010
Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor.
Microprocess. Microsystems, 2010

Application-Adaptive Reconfiguration of Memory Address Shuffler for FPGA-Embedded Instruction-Set Processor.
J. Circuits Syst. Comput., 2010

A Novel WI Decoder for the Segmented Frame Decoding in the Text-to-speech Synthesizer.
Proceedings of the SIGMAP 2010, 2010

Low latency variable length coding scheme for frame memory recompression.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010

2009
Thermal sensor allocation and placement for reconfigurable systems.
ACM Trans. Design Autom. Electr. Syst., 2009

Implmentation of digital audio effect SoC.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.
Proceedings of the FPL 2008, 2008

A 159.2mW SoC implementation of T-DMB receiver including stacked memories.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006
Design of Audio and Video decoder for the T-DMB Receiver.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

2004
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
IEEE Trans. Computers, 2004

Channel decoder architecture of OFDM based DMB system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An accurate evaluation of routing density for symmetrical FPGAs.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001


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