Chong-Min Kyung
Orcid: 0000-0002-3959-9714
According to our database1,
Chong-Min Kyung
authored at least 171 papers
between 1988 and 2022.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2009, "For contributions to system on chip processors".
Timeline
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On csauthors.net:
Bibliography
2022
Uniform Subdivision of Omnidirectional Camera Space for Efficient Spherical Stereo Matching.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
2021
A Memory- and Accuracy-Aware Gaussian Parameter-Based Stereo Matching Using Confidence Measure.
IEEE Trans. Pattern Anal. Mach. Intell., 2021
IEEE Access, 2021
2020
Resource-Efficient and High-Throughput VLSI Design of Global Optical Flow Method for Mobile Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 25th International Conference on Pattern Recognition, 2020
Proceedings of the 25th International Conference on Pattern Recognition, 2020
Proceedings of the 31st British Machine Vision Conference 2020, 2020
2019
IEEE Trans. Inf. Forensics Secur., 2019
IEEE Trans. Circuits Syst. Video Technol., 2019
Sensors, 2019
Design and Implementation of an Indoor Ambient Noise Monitoring System with Localization.
Proceedings of the 10th IEEE Annual Ubiquitous Computing, 2019
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019
2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems.
IEEE Trans. Circuits Syst. Video Technol., 2017
Lifetime Maximization of Wireless Video Sensor Network Node by Dynamically Resizing Communication Buffer.
KSII Trans. Internet Inf. Syst., 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017
2016
Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime.
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Content-Aware Video Encoding Scheme Based on Single-Pass Consistent Quality Control.
IEEE Trans. Broadcast., 2016
Memory efficient hardware accelerator for kernel support vector machine based pedestrian detection.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015
Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the IECON 2015, 2015
2014
Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
Dual frame rate motion detection for memory- and energy-constrained surveillance systems.
Proceedings of the 11th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2014
Proceedings of the 11th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Optimized learning rate for energy waste minimization in a background subtraction based surveillance system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the International Conference on Advances in Computing, 2013
2012
Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Energy-Aware Operation of Black Box Surveillance Cameras under Event Uncertainty and Memory Constraint.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012
2011
Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
An energy-aware hierarchical event detection in battery-operated wireless video surveillance systems.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
IEEE Trans. Multim., 2010
IEEE Trans. Circuits Syst. Video Technol., 2010
A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2010
A Dynamic Search Range Algorithm for Stabilized Reduction of Memory Traffic in Video Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2010
IEEE Trans. Circuits Syst. Video Technol., 2010
Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010
Event statistics and criticality-aware bitrate allocation to minimize energy consumption of memory-constrained wireless surveillance system.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010
A low cost single-pass fractional motion estimation architecture using bit clipping for H.264 video codec.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010
An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Selective Search Area Reuse Algorithm for Low External Memory Access Motion Estimation.
IEEE Trans. Circuits Syst. Video Technol., 2009
Lossless frame memory recompression for video codec preserving random accessibility of coding unit.
IEEE Trans. Consumer Electron., 2009
An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Energy-aware instruction-set customization for real-time embedded multiprocessor systems.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
A Multi-layer motion estimation scheme for spatial scalability in H.264/AVC scalable extension.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Suppressing rolling-shutter distortion of CMOS image sensors by motion vector detection.
IEEE Trans. Consumer Electron., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Data Reuse method between Heterogeneous Partitions (DRHP) in H.264/AVC motion compensator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead.
IEEE Trans. Computers, 2006
Three-Stage Clos-Network Switch Architecture with Buffered Center Stage for Multi-Class Traffic.
J. Circuits Syst. Comput., 2006
Improving Lookahead in Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction.
Proceedings of the 20th IEEE/ACM/SCS Workshop on Principles of Advanced and Distributed Simulation, 2006
2005
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
J. Circuits Syst. Comput., 2005
J. Circuits Syst. Comput., 2005
Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Computers, 2004
Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture.
Microprocess. Microsystems, 2004
IEEE Des. Test Comput., 2004
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 Design, 2004
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2002
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
J. Syst. Archit., 2002
An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Issues on the Interface Synthesis between Intellectual Properties Operating at Different Clock Frequencies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization.
Proceedings of the 2000 International Conference on Image Processing, 2000
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE International Conference on Communications: Global Convergence Through Communications, 2000
FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Fast development of source-level debugging system using hardware emulation (short paper).
Proceedings of ASP-DAC 2000, 2000
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics.
Proceedings of ASP-DAC 2000, 2000
1999
IEEE Trans. Consumer Electron., 1999
IEEE Trans. Computers, 1999
Microprocess. Microsystems, 1999
IEEE J. Solid State Circuits, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
1994
IEEE Trans. Computers, 1994
1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
A practical design method for instruction decoder PLAs for microprogrammed controllers.
Microprocess. Microsystems, 1993
1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
Circuit placement on arbitrarily shaped regions using the self-organization principle.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
Adaptive cluster growth: a new algorithm for circuit placement in rectilinear regions.
Comput. Aided Des., 1992
1991
J. Circuits Syst. Comput., 1991
A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
Proceedings of the 28th Design Automation Conference, 1991
1990
Proceedings of the Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region.
Proceedings of the European Design Automation Conference, 1990
1988