Ki-Seok Chung

Orcid: 0000-0002-2908-8443

According to our database1, Ki-Seok Chung authored at least 83 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2023
DiffusionVID: Denoising Object Boxes With Spatio-Temporal Conditioning for Video Object Detection.
IEEE Access, 2023

iNLC: Iterative Noisy Label Correction.
Proceedings of the 17th International Conference on Signal-Image Technology & Internet-Based Systems, 2023

Alert Refresh System for Mitigating RowHammer.
Proceedings of the 20th International SoC Design Conference, 2023

Dynamic Partitioning Method for Near-Memory Parallel Processing of Sparse Matrix-Vector Multiplication.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

Token Merging with Class Importance Score.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

An Efficient Noisy Label Learning Method with Semi-supervised Learning: An Efficient Noisy Label Learning Method with Semi-supervised Learning.
Proceedings of the 2023 6th International Conference on Machine Vision and Applications, 2023

2022
Regularized Convolutional Neural Network for Highly Effective Parallel Processing.
J. Comput. Sci. Eng., 2022

DAFA: Diversity-Aware Feature Aggregation for Attention-Based Video Object Detection.
IEEE Access, 2022

What Matters for Out-of-Distribution Detectors using Pre-trained CNN?
Proceedings of the 17th International Joint Conference on Computer Vision, 2022

2021
Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm.
KSII Trans. Internet Inf. Syst., 2021

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory.
IEEE Access, 2021

CLC: Noisy Label Correction via Curriculum Learning.
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2021

Robustness-Aware Filter Pruning for Robust Neural Networks Against Adversarial Attacks.
Proceedings of the 2021 IEEE 31st International Workshop on Machine Learning for Signal Processing (MLSP), 2021

EdgeRL: A Light-Weight C/C++ Framework for On-Device Reinforcement Learning.
Proceedings of the 18th International SoC Design Conference, 2021

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology.
Proceedings of the 18th International SoC Design Conference, 2021

Reducing Refresh Overhead with In-DRAM Error Correction Codes.
Proceedings of the 18th International SoC Design Conference, 2021

HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

FlowNetU: Accurate Uncertainty Estimation of Optical Flow for Video Object Detection.
Proceedings of the AIPR 2021: 4th International Conference on Artificial Intelligence and Pattern Recognition, Xiamen, China, September 24, 2021

2020
Direct Conversion: Accelerating Convolutional Neural Networks Utilizing Sparse Input Activation.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020

A Confidence-Calibrated MOBA Game Winner Predictor.
Proceedings of the IEEE Conference on Games, 2020

2019
GRAM: Gradient Rescaling Attention Model for Data Uncertainty Estimation in Single Image Super Resolution.
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

2018
Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers.
J. Circuits Syst. Comput., 2018

HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube.
IEEE Comput. Archit. Lett., 2018

Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Image Blending Techniques Based on GPU Acceleration.
Proceedings of the 2018 International Conference on Image and Graphics Processing, 2018

Implementation of a CNN accelerator on an Embedded SoC Platform using SDSoC.
Proceedings of the 2nd International Conference on Digital Signal Processing, 2018

Per-bank refresh with adaptive early termination for high density DRAM.
Proceedings of the 4th International Conference on Communication and Information Processing, 2018

Log-quantization on GRU networks.
Proceedings of the 4th International Conference on Communication and Information Processing, 2018

Efficient SIMD implementation for accelerating convolutional neural network.
Proceedings of the 4th International Conference on Communication and Information Processing, 2018

Optimization of FPGA-based LDPC decoder using high-level synthesis.
Proceedings of the 4th International Conference on Communication and Information Processing, 2018

2017
Self-Adaptive Termination Check of Min-Sum Algorithm for LDPC Decoders Using the First Two Minima.
KSII Trans. Internet Inf. Syst., 2017

CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube.
IEEE Comput. Archit. Lett., 2017

Modified Convolution Neural Network for Highly Effective Parallel Processing.
Proceedings of the 2017 IEEE International Conference on Information Reuse and Integration, 2017

2016
User-Centric Power Management for Embedded CPUs Using CPU Bandwidth Control.
IEEE Trans. Mob. Comput., 2016

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL.
KSII Trans. Internet Inf. Syst., 2016

Self-Adaptive Scaled Min-Sum Algorithm for LDPC Decoders Based on Delta-Min.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015
Conditional termination check min-sum algorithm for efficient LDPC decoders.
IEICE Electron. Express, 2015

Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Embedded GPUs.
IEEE Comput. Archit. Lett., 2015

Analysis of various DRAM devices from power consumption's perspective.
Proceedings of the 10th IEEE International Conference on Networking, 2015

Parallel LDPC decoding on a GPU using OpenCL and global memory for accelerators.
Proceedings of the 10th IEEE International Conference on Networking, 2015

2014
Design of OpenCL framework for embedded multi-core processors.
IEEE Trans. Consumer Electron., 2014

2013
Dynamic Power Management Technique for Multicore Based Embedded Mobile Devices.
IEEE Trans. Ind. Informatics, 2013

A Parallelization Technique with Integrated Multi-Threading for Video Decoding on Multi-core Systems.
KSII Trans. Internet Inf. Syst., 2013

Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation.
EURASIP J. Wirel. Commun. Netw., 2013

Novel level-up shifters for high performance and low power mobile devices.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2012
Ultra low power and high speed FPGA design with CNFET.
Proceedings of the International Symposium on Communications and Information Technologies, 2012

2011
Overlapped message passing technique with resource sharing for high speed CMMB LDPC decoder.
IEEE Trans. Consumer Electron., 2011

Multi-threaded syntax element partitioning for parallel entropy decoding.
IEEE Trans. Consumer Electron., 2011

A Technique for Fast Process Creation Based on Creation Location.
J. Comput. Sci. Eng., 2011

Parallel LDPC decoding using CUDA and OpenMP.
EURASIP J. Wirel. Commun. Netw., 2011

An adaptive low-power LDPC decoder using SNR estimation.
EURASIP J. Wirel. Commun. Netw., 2011

A Test Method for Power Management of SoC-based Microprocessors.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

FPGA implementation of unified kernel structure for MDCT/IMDCT in audio coding schemes.
Proceedings of the International SoC Design Conference, 2011

LDPC decoding for CMMB utilizing OpenMP and CUDA parallelization.
Proceedings of the IEEE 17th Asia-Pacific Conference on Communications, 2011

2010
Stage-based frame-partitioned parallelization of H.264/AVC decoding.
IEEE Trans. Consumer Electron., 2010

A predictive dynamic power management technique for embedded mobile devices.
IEEE Trans. Consumer Electron., 2010

2009
Thermal sensor allocation and placement for reconfigurable systems.
ACM Trans. Design Autom. Electr. Syst., 2009

Memory efficient multi-rate regular LDPC decoder for CMMB.
IEEE Trans. Consumer Electron., 2009

Thermal-Aware High-Level Synthesis Based on Network Flow Method.
J. Circuits Syst. Comput., 2009

A novel SoC platform based multi-IP verification and performance measurement.
Int. J. Inf. Commun. Technol., 2009

Optimisation of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding.
Int. J. Inf. Commun. Technol., 2009

Low Power MAC Design with Variable Precision Support.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

Performance evaluation of on-chip interconnect IP using CBR traffic generator model.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

2008
A unified power measurement and management platform for pipelined MPSoC executions.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Predictive power aware management for embedded mobile devices.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Timing driven force-directed floorplanning with incremental static timing analyzer.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
An incremental floorplanning algorithm for temperature reduction.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Design of Low Power MAC Operator with Dual Precision Mode.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

2004
Profile-based optimal intra-task voltage scheduling for hard real-time applications.
Proceedings of the 41th Design Automation Conference, 2004

2003
Properties of A1/BaTa2O6/GaN MIS Structure.
Proceedings of the International Conference on VLSI, 2003

2002
Synthesis and Optimization of Combinational Interface Circuits.
J. VLSI Signal Process., 2002

A Complete Model for Glitch Analysis in Logic Circuits.
J. Circuits Syst. Comput., 2002

Enhanced bus invert encodings for low-power.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
G-vector: A New Model for Glitch Analysis in Logic Circuits.
J. VLSI Signal Process., 2001

A Static Estimation Technique of Power Sensitivity in Logic Circuits.
Proceedings of the 38th Design Automation Conference, 2001

2000
Decomposition of Bus-Invert Coding for Low-Power I/O.
J. Circuits Syst. Comput., 2000

Behavioral-level partitioning for low power design in control-dominated application.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1998
Modeling and Synthesis of Combinational Logic Circuits: A Power Dissipation Perspective
PhD thesis, 1998

Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Low power multiplexer decomposition.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996
An algorithm for synthesis of system-level interface circuits.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1994
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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