Nick Kanopoulos

According to our database1, Nick Kanopoulos authored at least 25 papers between 1983 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.
Proceedings of the Integrated Circuit and System Design, 2004

Testability Concepts and DFT.
Proceedings of the VLSI Handbook., 1999

A dual rail circuits synthesis environment for the implementation of multiple output boolean functions.
I. J. Circuit Theory and Applications, 1998

An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.
I. J. Circuit Theory and Applications, 1995

Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction.
IEEE Computer, 1995

Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).
Proceedings of the Proceedings EURO-DAC'95, 1995

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations.
IEEE Trans. VLSI Syst., 1994

Multiple boundary scan-paths for minimizing circuit-board test-application time.
Microprocessing and Microprogramming, 1994

On the design of a high-performance, expandable, sorting engine.
Integr., 1994

Design and Implementation of a High-Performance, Modular, Sorting Engine.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Efficient board interconnect testing using the split boundary scan register.
J. Electronic Testing, 1993

Design of Self-Checking Circuits Using DCVS Logic: A Case Study.
IEEE Trans. Computers, 1992

A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port.
Microprocessing and Microprogramming, 1992

Design and implementation of a totally self-checking 16 × 16 bit array multiplier.
Integr., 1992

A new serial/parallel two's complement multiplier for vlsi digital signal processing.
I. J. Circuit Theory and Applications, 1992

The split boundary scan register technique for testing board interconnects.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

On Distributed Fault Simulation.
IEEE Computer, 1990

Creating the IC palette [ASIC design].
Proceedings of the First International Workshop on Rapid System Prototyping, 1990

The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability.
IEEE Computer, 1989

CAD Tools for Supporting System Design for Testability.
Proceedings of the Proceedings International Test Conference 1988, 1988

A High-Performance Single-Chip VLSI Signal Processor Architecture.
Proceedings of the VLSI Algorithms and Architectures, 1986

A single-chip adaptive delta modulator with optimum performance.
Integr., 1985

Testing of Bit-Serial Signal Processors.
Proceedings of the Proceedings International Test Conference 1983, 1983