Nick Kanopoulos

According to our database, Nick Kanopoulos authored at least 36 papers between 1983 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2004

Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.

Nick Kanopoulos

Proceedings of the Integrated Circuit and System Design, 2004

2000

Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures.

Kostas Adaos, George Alexiou, Nick Kanopoulos

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Testability Concepts and DFT.

Nick Kanopoulos

Proceedings of the VLSI Handbook., 1999

Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing.

Kostas Adaos, G. Ph. Alexiou, Nikos Kanopoulos

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

A dual rail circuits synthesis environment for the implementation of multiple output boolean functions.

Theodore Karoubalis, George Alexiou, Nick Kanopoulos

Int. J. Circuit Theory Appl., 1998

An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.

Kostas Adaos, George Alexiou, Nick Kanopoulos

Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

1996

TESPAD: a testability specifications advisor for a structured test methodology.

W. Weber, Michael G. McNamer, Nick Kanopoulos

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability.

Tassos Markas, E. Edwards, S. Wang, J. Medero, Nick Kanopoulos

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A versatile wireless system for real-time telemetry applications.

Theodoros Antonakopoulos, C. Powers, Nick Kanopoulos

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.

Theodore Karoubalis, Kostas Adaos, George Alexiou, Nick Kanopoulos

Int. J. Circuit Theory Appl., 1995

Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction.

Apostolos Dollas, Nick Kanopoulos

Computer, 1995

Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).

Theodore Karoubalis, George Alexiou, Nick Kanopoulos

Proceedings of the Proceedings EURO-DAC'95, 1995

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.

Jason P. Hurst, Nick Kanopoulos

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations.

Tassos Markas, Mark Royals, Nick Kanopoulos

IEEE Trans. Very Large Scale Integr. Syst., 1994

Multiple boundary scan-paths for minimizing circuit-board test-application time.

Theodoros Antonakopoulos, Nick Kanopoulos

Microprocess. Microprogramming, 1994

On the design of a high-performance, expandable, sorting engine.

George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos

Integr., 1994

Design and Implementation of a High-Performance, Modular, Sorting Engine.

George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Efficient board interconnect testing using the split boundary scan register.

Nazar S. Haider, Nick Kanopoulos

J. Electron. Test., 1993

1992

Design of Self-Checking Circuits Using DCVS Logic: A Case Study.

Nick Kanopoulos, Dimitris Pantzartzis, Frederick R. Bartram

IEEE Trans. Computers, 1992

A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port.

Mark Royals, Tassos Markas, Nick Kanopoulos

Microprocess. Microprogramming, 1992

Design and implementation of a totally self-checking 16 × 16 bit array multiplier.

Nick Kanopoulos, Joseph H. Carabetta

Integr., 1992

A new serial/parallel two's complement multiplier for vlsi digital signal processing.

George Alexiou, Nick Kanopoulos

Int. J. Circuit Theory Appl., 1992

The split boundary scan register technique for testing board interconnects.

Nazar S. Haider, Nick Kanopoulos

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1990

A bus-monitor unit for fault-tolerant system configurations.

Tassos Markas, Nick Kanopoulos

Microprocessing and Microprogramming, 1990

On Distributed Fault Simulation.

Tassos Markas, Mark Royals, Nick Kanopoulos

Computer, 1990

Creating the IC palette [ASIC design].

Mark Royals, Tassos Markas, Tianmaw Yang, Nick Kanopoulos

Proceedings of the First International Workshop on Rapid System Prototyping, 1990

1989

On the design of a real-time digital median filter.

J. Dodrill, Nick Kanopoulos

Microprocessing and Microprogramming, 1989

A built-in test module for fault isolation.

Nagesh Vasanthavada, Nick Kanopoulos

IEEE Des. Test, 1989

The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability.

Jill J. Hallenbeck, James R. Cybrynski, Nick Kanopoulos, Tassos Markas, Nagesh Vasanthavada

Computer, 1989

1988

Design of a bus-monitor for real-time applications.

Nick Kanopoulos, Peter N. Marinos

Microprocess. Microprogramming, 1988

CAD Tools for Supporting System Design for Testability.

Jill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson

Proceedings of the Proceedings International Test Conference 1988, 1988

1987

A monolithic scan-line bit producer for real-time image rasterization.

Nick Kanopoulos, Nagesh Vasanthavada

Microprocess. Microprogramming, 1987

1986

A High-Performance Single-Chip VLSI Signal Processor Architecture.

Nick Kanopoulos, Peter N. Marinos

Proceedings of the VLSI Algorithms and Architectures, 1986

1985

A single-chip adaptive delta modulator with optimum performance.

Nick Kanopoulos, Vassilios Makios

Integr., 1985

1984

Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors.

Nikos Kanopoulos, G. Thomas Mitchell

IEEE Des. Test, 1984

1983

Testing of Bit-Serial Signal Processors.

Nick Kanopoulos, G. Thomas Mitchell

Proceedings of the Proceedings International Test Conference 1983, 1983