George Alexiou
Orcid: 0000-0003-2244-4916Affiliations:
- University of Patras, Greece
According to our database1,
George Alexiou
authored at least 58 papers
between 1990 and 2022.
Collaborative distances:
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Bibliography
2022
CoRR, 2022
VisualFacts: A Platform for In-Situ Visual Exploration and Real-Time Entity Resolution.
Proceedings of the Workshops of the EDBT/ICDT 2022 Joint Conference, 2022
Proceedings of the IEEE International Conference on Big Data, 2022
2021
Simultaneous accessing of multiple SRAM subregions forming configurable and automatically generated memory fields.
Int. J. Circuit Theory Appl., 2021
2020
Int. J. Semantic Web Inf. Syst., 2020
Proceedings of the 32nd International Conference on Microelectronics, 2020
Lightweight Security Data Streaming, Based on Reconfigurable Logic, for FPGA Platform.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model.
J. Circuits Syst. Comput., 2019
Proceedings of the Information Search, Integration, and Personalization, 2019
2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Proceedings of the 23rd IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2018
2017
IEEE Commun. Mag., 2017
Computing, Caching, and Communication at the Edge: The Cornerstone for Building a Versatile 5G Ecosystem.
IEEE Commun. Mag., 2017
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017
Proceedings of the Research and Advanced Technology for Digital Libraries, 2017
2016
Int. J. Semantic Comput., 2016
Proceedings of the 2016 International Conference on Telecommunications and Multimedia, 2016
Proceedings of the 32nd IEEE International Conference on Data Engineering Workshops, 2016
2015
Schema-agnostic vs Schema-based Configurations for Blocking Methods on Homogeneous Data.
Proc. VLDB Endow., 2015
2014
Proceedings of the International Conference on Telecommunications and Multimedia, 2014
Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology.
Proceedings of the 18th Panhellenic Conference on Informatics, 2014
Proceedings of the 18th Panhellenic Conference on Informatics, 2014
LinkZoo: A Linked Data Platform for Collaborative Management of Heterogeneous Resources.
Proceedings of the Semantic Web: ESWC 2014 Satellite Events, 2014
Proceedings of the 19th IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2014
Proceedings of the 19th IEEE International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, 2014
2012
Intelligent and Semantic Real-Time Process of the Greek LOD for Enhancing Citizen Awareness in Public Expenditures.
Proceedings of the Web Information Systems Engineering - WISE 2012, 2012
Proceedings of the 2012 International Conference on Telecommunications and Multimedia, 2012
2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Microelectron. J., 2008
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008
Proceedings of the Panhellenic Conference on Informatics, 2008
2007
Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection System.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
A wireless infrared sensor network for the estimation of the position and orientation of a moving target.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007
Utilising noise effects on infrared pattern reception for position estimation on a grid plane.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007
2006
A core generator for arithmetic cores and testing structures with a network interface.
J. Syst. Archit., 2006
Position Estimation on a Grid, Based on Infrared Pattern Reception Features.
Proceedings of the Ubiquitous Computing, 2006
2004
New Challenges Emerging on the Design of VLSI Circuits Made of MOSFETs Using New Gate Dielectric Materials.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
2002
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.
J. Syst. Archit., 2002
2001
VLSI Design, 2001
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1999
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
1998
A dual rail circuits synthesis environment for the implementation of multiple output boolean functions.
Int. J. Circuit Theory Appl., 1998
An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
1996
J. Circuits Syst. Comput., 1996
1995
A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.
Int. J. Circuit Theory Appl., 1995
Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1992
A new serial/parallel two's complement multiplier for vlsi digital signal processing.
Int. J. Circuit Theory Appl., 1992
1990