Nitish Satya Murthy

Orcid: 0000-0003-0181-8069

According to our database1, Nitish Satya Murthy authored at least 6 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

2024
Optimization of block-scaled integer GeMMs for efficient DNN deployment on scalable in-order vector processors.
J. Syst. Archit., 2024

Efficient DNN Training Using Vectorized Block-Scaled GeMMs with Adaptive Block Shapes.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design - 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Adaptive Block-Scaled GeMMs on Vector Processors for DNN Training at the Edge.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

2023
Quantized Dynamics Models for Hardware-Efficient Control and Planning in Model-Based RL.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2023

2022
Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge.
Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022


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