Xiaoling Yi

According to our database, Xiaoling Yi authored at least 19 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

An Analytical Model for Performance-Carbon Co-Optimization of Edge AI Accelerators.

Jiacong Sun, Xiaoling Yi, Arne Symons, Georges G. E. Gielen, Lieven Eeckhout, Marian Verhelst

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026

A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access.

Xiaoling Yi, Ryan Antonio, Yunhao Deng, Fanchen Kong, Joren Dumoulin, Jun Yin, Marian Verhelst

CoRR, February, 2026

Fine-Grained Classification for Depth Estimation From Monocular Microscopy for Robotic Micromanipulation of Motile Cells.

Han Yang, Yufei Jin, Aojun Jiang, Xinrui Wang, Xibu Wang, Xiaoling Yi, Yu Sun, Zhuoran Zhang

IEEE Robotics Autom. Lett., January, 2026

The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead.

Josse Van Delm, Anton Lydike, Joren Dumoulin, Jonas Crols, Xiaoling Yi, Ryan Antonio, Jackson Woodruff, Tobias Grosser, Marian Verhelst

Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

Precision-Scalable Microscaling Datapaths with Optimized Reduction Tree for Efficient NPU Integration.

Stef Cuyckens, Xiaoling Yi, Robin Geens, Joren Dumoulin, Martin Wiesner, Chao Fang, Marian Verhelst

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

Torrent: A Distributed DMA for Efficient and Flexible Point-to-Multipoint Data Movement.

Yunhao Deng, Fanchen Kong, Xiaoling Yi, Ryan Antonio, Marian Verhelst

CoRR, December, 2025

Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning.

Zheng Wu, Jinyi Shen, Xiaoling Yi, Li Shang, Fan Yang, Xuan Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

Flexible Hardware Accelerators for Ultra-Low Power Edge AI: The CONVOLVE Approach.

Panagiotis Chaidos, Alexios Maras, Georgios Alexandris, Xiaoling Yi, Asmae El Arrassi, Bas Ahn, James D. Garside, Yunhao Deng, Theofilos Spyrou, Anteneh Gebregiorgis, Mottaqiallah Taouil, Manil Dev Gomony, Sotirios Xydis, Marian Verhelst, Said Hamdioui, Dimitrios Soudris, Henk Corporaal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning.

Stef Cuyckens, Xiaoling Yi, Nitish Satya Murthy, Chao Fang, Marian Verhelst

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems.

Ryan Antonio, Joren Dumoulin, Xiaoling Yi, Josse Van Delm, Yunhao Deng, Guilherme Paim, Marian Verhelst

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2025

XDMA: A Distributed, Extensible DMA Architecture for Layout-Flexible Data Movements in Heterogeneous Multi-Accelerator SoCs.

Fanchen Kong, Yunhao Deng, Xiaoling Yi, Ryan Antonio, Marian Verhelst

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators.

Xiaoling Yi, Yunhao Deng, Ryan Antonio, Fanchen Kong, Guilherme Paim, Marian Verhelst

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.

Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Pereira Paim, Marian Verhelst

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling.

Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm, Guilherme Paim, Marian Verhelst

CoRR, 2024

SenseDSE: Sensitivity-Based Performance Evaluation for Design Space Exploration of Microarchitecture.

Zheng Wu, Xiaoling Yi, Li Shang, Fan Yang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

TPNoC: An Efficient Topology Reconfigurable NoC Generator.

Jiangnan Yu, Fan Yang, Xiaoling Yi, Chixiao Chen, Jun Tao, Dong Xu, Xiankui Xiong, Haitao Yang

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Graph Representation Learning for Microarchitecture Design Space Exploration.

Xiaoling Yi, Jialin Lu, Xiankui Xiong, Dong Xu, Li Shang, Fan Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.

Xiaoling Yi, Jiangnan Yu, Zheng Wu, Xiankui Xiong, Dong Xu, Chixiao Chen, Jun Tao, Fan Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Automated Compiler for RISC-V Based DNN Accelerator.

Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao, Fan Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022