Debjyoti Bhattacharjee

Orcid: 0000-0001-6561-8934

According to our database1, Debjyoti Bhattacharjee authored at least 45 papers between 2014 and 2023.

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Bibliography

2023
Improved Linear Decomposition of Majority and Threshold Boolean Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge.
IEEE J. Solid State Circuits, 2023

AIMC Modeling and Parameter Tuning for Layer-Wise Optimal Operating Point in DNN Inference.
IEEE Access, 2023

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
In-memory realization of SHA-2 using ReVAMP architecture.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Perspectives on Emerging Computation-in-Memory Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Crossbar-Constrained Technology Mapping for ReRAM Based In-Memory Computing.
IEEE Trans. Computers, 2020

Efficient Quantum Circuits for Square-Root and Inverse Square-Root.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
New techniques for fault-tolerant decomposition of Multi-Controlled Toffoli gate.
CoRR, 2019

Accelerating Binary-Matrix Multiplication on FPGA.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Architectures and automation for beyond-CMOS technologies
PhD thesis, 2018

Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays.
ACM J. Emerg. Technol. Comput. Syst., 2018

Quantum Circuits for Toom-Cook Multiplication.
CoRR, 2018

Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

ReRAM-based In-Memory Computation of Galois Field arithmetic.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Synthesis, Technology Mapping and Optimization for Emerging Technologies.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Synthesis of Multi-valued Literal Using Lukasiewicz Logic.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Technology-aware logic synthesis for ReRAM based in-memory computing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Efficient complementary resistive switch-based crossbar array Booth multiplier.
Microelectron. J., 2017

Depth-Optimal Quantum Circuit Placement for Arbitrary Topologies.
CoRR, 2017

Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

SHA-3 implementation using ReRAM based in-memory computing architecture.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

ReVAMP: ReRAM based VLIW architecture for in-memory computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Area-constrained technology mapping for in-memory computing using ReRAM devices.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Hardware Accelerator for Stream Cipher Spritz.
Proceedings of the 13th International Joint Conference on e-Business and Telecommunications (ICETE 2016), 2016

Efficient implementation of multiplexer and priority multiplexer using 1S1R ReRAM crossbar arrays.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Delay-optimal technology mapping for in-memory computing using ReRAM devices.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Ensemble Classifier based approach for Code-Mixed Cross-Script Question Classification.
Proceedings of the Working notes of FIRE 2016, 2016

EAST: Efficient Assertion Simulation techniques.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Comparison Between an HVS Inspired Linear Filter and the Bilateral Filter in Performing "Vision at a Glance" through Smoothing with Edge Preservation.
Int. J. Image Graph., 2015

EvoDeb: Debugging Evolving Hardware Designs.
Proceedings of the 28th International Conference on VLSI Design, 2015

2014
Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption.
Proceedings of the Information Security and Cryptology - 10th International Conference, 2014


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