Nripendra N. Biswas

According to our database1, Nripendra N. Biswas authored at least 28 papers between 1970 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

1996
Cubical CAMP for minimization of Boolean functions.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1993
Logic design theory.
Prentice Hall, ISBN: 978-0-13-010695-7, 1993

1992
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures.
IEEE Trans. Computers, 1992

1990
On covering distant minterms by the camp algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Further Comments on "Detection of Faults in Programmable Logic Arrays".
IEEE Trans. Computers, 1990

A Reconfigurable Tree Architecture with Multistage Interconnection Network.
IEEE Trans. Computers, 1990

1989
An algorithm for multiple output minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs.
IEEE Trans. Computers, 1988

1987
A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture.
SIGARCH Comput. Archit. News, 1987

Simple methods for the calculation of root of a reconfigurable binary tree structure.
Proc. IEEE, 1987

1986
Computer-Aided Minimization Procedure for Boolean Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1985
On Bit Steering in the Minimization of the Control Memory of Microprogrammed Processors.
IEEE Trans. Computers, 1985

: A Testable PLA Design with Minimal Hardware and Test Set.
Proceedings of the Proceedings International Test Conference 1985, 1985

Multiple output minimization.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1983
On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer.
IEEE Trans. Computers, 1983

A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays.
IEEE Trans. Computers, 1983

An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays.
IEEE Trans. Computers, 1983

1982
A Design for Complete Testability of Programmable Logic Arrays.
Proceedings of the Proceedings International Test Conference 1982, 1982

1981
Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers.
IEEE Trans. Computers, 1981

1980
Optimal Interconnections in the Design of Microprocessors and Digital Systems.
IEEE Trans. Computers, 1980

1979
A New Approach to 2-Asummability Testing.
IEEE Trans. Computers, 1979

1977
An Algorithm for Testing 2-Asummability of Boolean Functions.
IEEE Trans. Computers, 1977

1976
Further Comments on "Closure Partition Method for Minimizing Incomplete Sequential Machines".
IEEE Trans. Computers, 1976

1975
Minimization of Incompletely Specified Sequential Machines.
IEEE Trans. Computers, 1975

1974
State Minimization of Incompletely Specified Sequential Machines.
IEEE Trans. Computers, 1974

1973
Comments on "Identification of Totally Symmetric Boolean Functions".
IEEE Trans. Computers, 1973

1971
Minimization of Boolean Functions.
IEEE Trans. Computers, 1971

1970
On Identification of Totally Symmetric Boolean Functions.
IEEE Trans. Computers, 1970


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