James Jacob

According to our database1, James Jacob authored at least 22 papers between 1985 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Improving spatial transferability of ecological niche model of Hevea brasiliensis using pooled occurrences of introduced ranges in two biogeographic regions of India.
Ecol. Informatics, 2016

2000
Line coverage of path delay faults.
IEEE Trans. Very Large Scale Integr. Syst., 2000

1998
A Fast Two-level Logic Minimizer.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Optimizing Logic Design Using Boolean Transforms.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
A Novel Path Delay Fault Simulator Using Binary Logic.
VLSI Design, 1996

Functional test generation for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

On test coverage of path delay faults.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Cubical CAMP for minimization of Boolean functions.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Lossless Compression Of Images Using Logic Minimization.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

1995
Switching theoretic approach to image compression.
Signal Process., 1995

Functional test generation for non-scan sequential circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

An efficient automatic test generation system for path delay faults in combinational circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Logic minimization based approach for compressing image data.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994
An Improved Deductive Fault Simulator.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
Multiple fault detection in two-level multi-output circuits.
J. Electron. Test., 1992

An Efficient Rule Based Fault Simulator.
Proceedings of the Fifth International Conference on VLSI Design, 1992

Functional Test Generation for Sequential Circuits.
Proceedings of the Fifth International Conference on VLSI Design, 1992

Finite State Machine Testing Based on Growth and Dissappearance Faults.
Proceedings of the Digest of Papers: FTCS-22, 1992

1990
Further Comments on "Detection of Faults in Programmable Logic Arrays".
IEEE Trans. Computers, 1990

1985
: A Testable PLA Design with Minimal Hardware and Test Set.
Proceedings of the Proceedings International Test Conference 1985, 1985


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