Palash Das

According to our database, Palash Das authored at least 18 papers between 2014 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Enhanced Prefetching via Dynamic Multistep SARSA-Based Reinforcement Learning.

Satyaswaroop Nayak, Anadi Goyal, Sheel Sindhu Manohar, Dip Sankar Banerjee, Palash Das

IEEE Embed. Syst. Lett., April, 2026

GateAttn-ViT: Entropy-gated, attention-guided token pruning for resource-efficient Vision Transformer acceleration on FPGAs.

Akshansh Yadav, Palash Das

J. Syst. Archit., 2026

Exploiting virtual channel allocation policies in STT-RAM buffers of NoC routers through hardware Trojan.

Josna Philomina, Rekha K. James, Palash Das, Shirshendu Das, Daleesha M. Viswanathan

J. Syst. Archit., 2026

NeSTAR: Hardware Trojans and its mitigation strategy in NoC routers.

Josna Philomina, Rekha K. James, Shirshendu Das, Palash Das, Daleesha M. Viswanathan

Integr., 2026

Exploring Bit-Flip Attacks on DQNs with a Hash-Driven Defense Accelerator.

Om Chandra Sharma, Anmol Yadav, Vihan Sachin Karnik, Palash Das

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025

Hybrid Token Selector based Accelerator for ViTs.

Akshansh Yadav, Anadi Goyal, Palash Das

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2023

edAttack: Hardware Trojan Attack on On-Chip Packet Compression.

Atul Kumar, Dipika Deb, Shirshendu Das, Palash Das

IEEE Des. Test, December, 2023

ALAMNI: Adaptive LookAside Memory Based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time.

Palash Das, Shashank Sharma, Hemangee K. Kapoor

IEEE Trans. Computers, March, 2023

NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism.

Palash Das, Hemangee K. Kapoor

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

ZaLoBI: Zero avoiding Load Balanced Inference accelerator.

Imlijungla Longchar, Palash Das, Hemangee K. Kapoor

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Hydra: A near hybrid memory accelerator for CNN inference.

Palash Das, Ajay Joshi, Hemangee K. Kapoor

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs.

Palash Das, Hemangee K. Kapoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks.

Palash Das, Hemangee K. Kapoor

ACM J. Emerg. Technol. Comput. Syst., 2021

2020

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors.

Chirag Joshi, Palash Das, Ashwini A. Kulkarni, Hemangee K. Kapoor

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2018

Towards Near Data Processing of Convolutional Neural Networks.

Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory.

Palash Das, Hemangee K. Kapoor

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2014

A comprehensive fault diagnosis technique for reversible logic circuits.

Bikromadittya Mondal, Palash Das, Pradyut Sarkar, Susanta Chakraborty

Comput. Electr. Eng., 2014

Signature analysis for synthesis of reversible circuit.

Palash Das, Bikromadittya Mondal

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014