Sheel Sindhu Manohar

Orcid: 0000-0001-7490-6209

According to our database1, Sheel Sindhu Manohar authored at least 5 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

2022
CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches.
ACM Trans. Embed. Comput. Syst., 2022

2019
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation.
J. Syst. Archit., 2019

Refresh optimised embedded-dram caches based on zero data detection.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019


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