Daniel Palmer Dabbelt

According to our database1, Daniel Palmer Dabbelt authored at least 7 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2017
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017

Cyclist: Accelerating hardware development.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V.
CoRR, 2016

Vector Processors for Energy-Efficient Embedded Systems.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016


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