Ben Keller

According to our database1, Ben Keller authored at least 29 papers between 1995 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.
Proceedings of the MLCAD '22: 2022 ACM/IEEE Workshop on Machine Learning for CAD, Virtual Event China, September 12, 2022

2021
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.
CoRR, 2021

Simba: scaling deep-learning inference with chiplet-based architecture.
Commun. ACM, 2021

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Accelerating Chip Design With Machine Learning.
IEEE Micro, 2020

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.
IEEE J. Solid State Circuits, 2020

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.
CoRR, 2020

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

PRIMAL: Power Inference using Machine Learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2017
Energy-Efficient System Design Through Adaptive Voltage Scaling.
PhD thesis, 2017

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017

2016
An Agile Approach to Building RISC-V Microprocessors.
IEEE Micro, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015

A Method for the Systematic Generation of Audit Logs in a Digital Preservation Environment and Its Experimental Implementation In a Production Ready System.
Proceedings of the 12th International Conference on Digital Preservation, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

A Pausible Bisynchronous FIFO for GALS Systems.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

1995
Reply to discussion by B. Keller and R. Nance.
J. Softw. Maintenance Res. Pract., 1995


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