Jaehwa Kwak

According to our database, Jaehwa Kwak authored at least 12 papers between 2011 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Multi-Scale Contrastive-Adversarial Distillation for Super-Resolution.

Donggeun Ko, Youngsang Kwak, San Kim, Jaehwa Kwak, Jaekwang Kim

Proceedings of the IEEE/CVF International Conference on Computer Vision, ICCV 2025, 2025

2021

Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling.

Rafael C. F. Sousa, Byungmin Jung, Jaehwa Kwak, Michael Frank, Guido Araujo

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2020

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

John Charles Wright, Colin Schmidt, Ben Keller, Daniel Palmer Dabbelt, Jaehwa Kwak, Vighnesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Borivoje Nikolic

IEEE Trans. Very Large Scale Integr. Syst., 2020

2017

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.

Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee, Milovan Blagojevic, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic

IEEE J. Solid State Circuits, 2017

2016

An Agile Approach to Building RISC-V Microprocessors.

Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic

IEEE Micro, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic

IEEE J. Solid State Circuits, 2016

A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI.

Jaehwa Kwak, Borivoje Nikolic

IEEE J. Solid State Circuits, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.

Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic

Proceedings of the Symposium on VLSI Circuits, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.

Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

A 550-2260MHz self-adjustable clock generator in 28nm FDSOI.

Jaehwa Kwak, Borivoje Nikolic

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2011

Technology Variability From a Design Perspective.

Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos

IEEE Trans. Circuits Syst. I Regul. Pap., 2011