Jaehwa Kwak

Orcid: 0000-0002-8045-1404

According to our database1, Jaehwa Kwak authored at least 11 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2021
Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2017
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017

2016
An Agile Approach to Building RISC-V Microprocessors.
IEEE Micro, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

A 550-2260MHz self-adjustable clock generator in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2011
Technology Variability From a Design Perspective.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011


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