Paolo Zicari

Orcid: 0000-0002-9119-9865

According to our database¹, Paolo Zicari authored at least 21 papers between 2005 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Other

Bibliography

2023

An Explainable Deep Ensemble Framework for Intelligent Ticket Management.

[BibT_eX]

[DOI]

ERCIM News, 2023

Learning Deep Fake-News Detectors from Scarcely-Labelled News Corpora.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Enterprise Information Systems, 2023

2022

Combining deep ensemble learning and explanation for intelligent ticket management.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2022

2021

Discovering accurate deep learning based predictive models for automatic customer support ticket classification.

[BibT_eX]

[DOI]

Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

2017

Controversy-Aware Hybrid Trust Inference in Online Social Networks.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

2016

Controversy in Trust Networks.

[BibT_eX]

[DOI]

Proceedings of the Trust and Trustworthy Computing - 9th International Conference, 2016

2014

A power-efficient real-time architecture for SURF feature extraction.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013

Efficient and high performance FPGA-based rectification architecture for stereo vision.

[BibT_eX]

[DOI]

Paolo Zicari

Microprocess. Microsystems, 2013

2012

Low-cost FPGA stereo vision system for real time disparity maps calculation.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

An embedded system for on field testing of human identification using ECG biometric.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Information Science, 2012

2010

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

2009

Designing High-Speed Adders in Power-Constrained Environments.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Low-power split-path data-driven dynamic logic.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2009

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

A matrix product accelerator for field programmable systems on chip.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2008

2007

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

I systems on programmable chip.

[BibT_eX]

[DOI]

Paolo Zicari

PhD thesis, 2006

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs.

[BibT_eX]

[DOI]

Paolo Zicari

Pasquale Corsonello

Stefania Perri

Proceedings of the 13th IEEE International Conference on Electronics, 2006

SAD-Based Stereo Matching Circuit for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

Microprocessor-based FPGA implementation of SPIHT image compression subsystems.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2005

Paolo Zicari

Timeline

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