Fabio Frustaci
Orcid: 0000-0001-5795-4321
According to our database1,
Fabio Frustaci
authored at least 54 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
IEEE Access, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes.
Sensors, 2022
Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators.
AII, 2022
An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm Implementation in Wearable Embedded Systems.
AII, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation.
IEEE Trans. Circuits Syst., 2020
J. Real Time Image Process., 2020
IET Circuits Devices Syst., 2020
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
J. Real Time Image Process., 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Microprocess. Microsystems, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015
Integr., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations.
Int. J. Circuit Theory Appl., 2014
Circuits Syst. Signal Process., 2014
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A novel background subtraction method based on color invariants and grayscale levels.
Proceedings of the International Carnahan Conference on Security Technology, 2014
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Microelectron. Reliab., 2012
Int. J. Circuit Theory Appl., 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.
ACM Trans. Reconfigurable Technol. Syst., 2010
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
IET Circuits Devices Syst., 2008
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Leakage energy reduction techniques in deep submicron cache memories: a comparative study.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006