Marco Lanuzza
Orcid: 0000-0002-6480-9218Affiliations:
- University of Calabria, Department of Computer Engineering, Cosenza, Italy
According to our database1,
Marco Lanuzza
authored at least 96 papers
between 2004 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Access, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing.
IEEE Access, 2023
Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach.
IEEE Access, 2023
A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation.
IEEE Access, 2023
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V.
IEEE Access, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm.
IEEE J. Solid State Circuits, 2022
A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion.
CoRR, 2022
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing.
CoRR, 2022
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs.
CoRR, 2022
All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification.
IEEE Access, 2022
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification.
IEEE Access, 2022
Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW.
IEEE J. Solid State Circuits, 2021
Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications.
CoRR, 2021
Proceedings of the IEEE International Conference on Smart Internet of Things, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework.
Integr., 2020
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm<sup>2</sup> Area in 180nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions.
Proceedings of the Internet and Distributed Computing Systems, 2019
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A portable class of 3-transistor current references with low-power sub-0.5 V operation.
Int. J. Circuit Theory Appl., 2018
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations.
Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Int. J. Circuit Theory Appl., 2017
Int. J. Circuit Theory Appl., 2017
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2016
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits.
VLSI Design, 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.
Int. J. Circuit Theory Appl., 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.
Int. J. Circuit Theory Appl., 2014
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations.
Int. J. Circuit Theory Appl., 2014
Int. J. Circuit Theory Appl., 2014
Circuits Syst. Signal Process., 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
2013
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops.
J. Low Power Electron., 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Microelectron. Reliab., 2012
Int. J. Circuit Theory Appl., 2012
2010
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.
ACM Trans. Reconfigurable Technol. Syst., 2010
J. Low Power Electron., 2010
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron., 2009
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
2007
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
IEEE Trans. Circuits Syst. Video Technol., 2006
2005
Progetto e realizzazione VLSI di circuiti aritmetici ottimizzati per applicazioni multimediali.
PhD thesis, 2005
Microprocess. Microsystems, 2005
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004