Marco Lanuzza

Affiliations:
  • University of Calabria, Department of Computer Engineering, Cosenza, Italy


According to our database1, Marco Lanuzza authored at least 68 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework.
Integr., 2020

A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm<sup>2</sup> Area in 180nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI.
IEEE J. Solid State Circuits, 2019

Double-precision Dual Mode Logic carry-save multiplier.
Integr., 2019

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs.
Proceedings of the 16th International Conference on Synthesis, 2019

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions.
Proceedings of the Internet and Distributed Computing Systems, 2019

An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A portable class of 3-transistor current references with low-power sub-0.5 V operation.
Int. J. Circuit Theory Appl., 2018

Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations.
Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018

Design of a 3T current reference for low-voltage, low-power operation.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017
An Ultralow-Voltage Energy-Efficient Level Shifter.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A physical unclonable function based on a 2-transistor subthreshold voltage divider.
Int. J. Circuit Theory Appl., 2017

Low energy/delay overhead level shifter for wide-range voltage conversion.
Int. J. Circuit Theory Appl., 2017

Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework.
Proceedings of the 14th International Conference on Synthesis, 2017

Evaluation of Dual Mode Logic in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A variation-aware simulation framework for hybrid CMOS/spintronic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of a sub-1-V nanopower CMOS current reference.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits.
VLSI Design, 2015

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.
Int. J. Circuit Theory Appl., 2015

2014
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.
Int. J. Circuit Theory Appl., 2014

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations.
Int. J. Circuit Theory Appl., 2014

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates.
Int. J. Circuit Theory Appl., 2014

Designing Dynamic Carry Skip Adders: Analysis and Comparison.
Circuits Syst. Signal Process., 2014

Dynamic gate-level body biasing for subthreshold digital design.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Improving speed and power characteristics of pulse-triggered flip-flops.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops.
J. Low Power Electron., 2013

2012
Low-Power Level Shifter for Multi-Supply Voltage Designs.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Comparative analysis of yield optimized pulsed flip-flops.
Microelectron. Reliab., 2012

Energy-efficient single-clock-cycle binary comparator.
Int. J. Circuit Theory Appl., 2012

2010
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications.
ACM Trans. Reconfigurable Technol. Syst., 2010

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder.
J. Low Power Electron., 2010

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A new low-power high-speed single-clock-cycle binary comparator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Impact of Random Process Variations on Different 65nm SRAM Cell Topologies.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

2009
Designing High-Speed Adders in Power-Constrained Environments.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron., 2009

Low-power split-path data-driven dynamic logic.
IET Circuits Devices Syst., 2009

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

New performance/power/area efficient, reliable full adder design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Design and Implementation of a 90nm Low bit-rate Image Compression Core.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Technol., 2006

2005
A high-performance fully reconfigurable FPGA-based 2D convolution processor.
Microprocess. Microsystems, 2005

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Variable precision arithmetic circuits for FPGA-based multimedia processors.
IEEE Trans. Very Large Scale Integr. Syst., 2004


  Loading...