Giuseppe Cocorullo

According to our database1, Giuseppe Cocorullo authored at least 42 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Bibliography

2019
Multimodal background subtraction for high-performance embedded systems.
J. Real Time Image Process., 2019

2018
A Smart Torque Control for a High Efficiency 4WD Electric Vehicle.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
An efficient hardware-oriented stereo matching algorithm.
Microprocess. Microsystems, 2016

Design of efficient QCA multiplexers.
Int. J. Circuit Theory Appl., 2016

2014
Area-Delay Efficient Binary Adders in QCA.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A novel background subtraction method based on color invariants and grayscale levels.
Proceedings of the International Carnahan Conference on Security Technology, 2014

2013
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm.
Comput. Vis. Image Underst., 2013

2012
Low-cost FPGA stereo vision system for real time disparity maps calculation.
Microprocess. Microsystems, 2012

Design approach for high-bandwidth low-power three-stage operational amplifiers.
Int. J. Circuit Theory Appl., 2012

2010
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance.
Microelectron. J., 2010

2009
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A matrix product accelerator for field programmable systems on chip.
Microprocess. Microsystems, 2008

High-performance noise-tolerant circuit techniques for CMOS dynamic logic.
IET Circuits Devices Syst., 2008

Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Settling Time Minimization of Operational Amplifiers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Design methodology of nested-Miller amplifiers for small capacitive loads.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Design and Implementation of a 90nm Low bit-rate Image Compression Core.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Technol., 2006

Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Leakage energy reduction techniques in deep submicron cache memories: a comparative study.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A high-performance fully reconfigurable FPGA-based 2D convolution processor.
Microprocess. Microsystems, 2005

Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
Microprocess. Microsystems, 2005

Fast Low-Power 64-Bit Modular Hybrid Adder.
Proceedings of the Integrated Circuit and System Design, 2005

Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
Proceedings of the Integrated Circuit and System Design, 2005

2004
Variable precision arithmetic circuits for FPGA-based multimedia processors.
IEEE Trans. Very Large Scale Integr. Syst., 2004

2003
A high-speed energy-efficient 64-bit reconfigurable binary adder.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
VLSI circuits for low-power high-speed asynchronous addition.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
CMOS sizing rule for high performance long interconnects.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.
Proceedings of the Integrated Circuit Design, 2000

Designing High-Speed Asynchronous Pipelines.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
High performance VLSI modules for division and square root.
Microprocess. Microsystems, 1998


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