Simon W. Moore

Orcid: 0000-0002-2806-495X

Affiliations:
  • University of Cambridge, UK


According to our database1, Simon W. Moore authored at least 88 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection.
IEEE Des. Test, February, 2024

2023
How Flexible Is CXL's Memory Protection?
Commun. ACM, December, 2023

POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture.
ACM Trans. Parallel Comput., June, 2023

How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel.
ACM Queue, 2023

The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System.
IEEE Micro, 2023

CHERIoT: Complete Memory Safety for Embedded Devices.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Towards xBGAS on CHERI: Supporting a Secure Global Memory.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Architectural Contracts for Safe Speculation.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022
Practical Distributed Implementation of Very Large Scale Petri Net Simulations.
Trans. Petri Nets Other Model. Concurr., 2022

Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture.
IET Comput. Digit. Tech., 2022

CompartOS: CHERI Compartmentalization for Embedded Systems.
CoRR, 2022

Non-deterministic event brokered computing.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

2021
General hardware multicasting for fine-grained message-passing architectures.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2020
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020


Position Paper: Defending Direct Memory Access with CHERI Capabilities.
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation.
Proceedings of the CYSARM@CCS '20: Proceedings of the 2nd Workshop on Cyber-Security Arms Race, 2020

Termination detection for fine-grained message-passing architectures.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
CHERI Concentrate: Practical Compressed Capabilities.
IEEE Trans. Computers, 2019

Through computer architecture, darkly.
Commun. ACM, 2019

Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals.
Proceedings of the 26th Annual Network and Distributed System Security Symposium, 2019

CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Tinsel: A Manythread Overlay for FPGA Clusters.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

2017
Programming Model to Develop Supercomputer Combinatorial Solvers.
Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017


CHERI JNI: Sinking the Java Security Model into the C.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Fast Protection-Domain Crossing in the CHERI Capability-System Architecture.
IEEE Micro, 2016

CHERI: A Hardware-Software System to Support the Principle of Least Privilege.
ERCIM News, 2016

A consistency checker for memory subsystem traces.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Conquering the complexity mountain: Full-stack computer architecture teaching with FPGAs.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015
CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

A generic synthesisable test bench.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
Power Optimized Transceivers for Future Switched Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Reliably prototyping large SoCs using FPGA clusters.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

The CHERI capability model: Revisiting RISC in an age of risk.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Rapid codesign of a soft vector processor and its compiler.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Interconnect for commodity FPGA clusters: Standardized or customized?
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors.
IEEE Trans. Computers, 2013

A 64-bit MIPS processor running freebsd on a portable FPGA tablet.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Managing the FPGA memory wall: Custom computing or vector processing?
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A spiking neural network on a portable FPGA tablet.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Energy Implications of Photonic Networks With Speculative Transmission.
JOCN, 2012

Mamba: A scalable communication centric multi-threaded processor architecture.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2010
Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits.
PLoS Comput. Biol., 2010

Proximity coherence for chip multiprocessors.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
An Energy and Performance Exploration of Network-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Implications of Electronics Technology Trends for Algorithm Design.
Comput. J., 2009

Flow-aware allocation for on-chip networks.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A communication characterisation of Splash-2 and Parsec.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008
Fractal communication in software data dependency graphs.
Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

The next resource war: computation vs. communication.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

A Network of Time-Division Multiplexed Wiring for FPGAs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Exploring hard and soft networks-on-chip for FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Tamper Protection for Security Devices.
Proceedings of the 2008 ECSIS Symposium on Bio-inspired, 2008

Implications of Electronics Technology Trends to Algorithm Design.
Proceedings of the Visions of Computer Science, 2008

2007
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Power and Energy Exploration of Network-on-Chip Architectures.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Demystifying Data-Driven and Pausible Clocking Schemes.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
An Asynchronous Interconnect Architecture for Device Security Enhancement.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Adding question answering to an e-tutor for programming languages.
Proceedings of the Applications and Innovations in Intelligent Systems XIV, 2006

An area-efficient, pulse-based interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

RasP: An Area-efficient, On-chip Network.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

An Asynchronous PLA with Improved Security Characteristics.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Implementing Cryptography on TFT Technology for Secure Display Applications.
Proceedings of the Smart Card Research and Advanced Applications, 2006

The design and implementation of a low-latency on-chip network.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

My Compiler Really Understands Me: An Adaptive Programming Language Tutor.
Proceedings of the Adaptive Hypermedia and Adaptive Web-Based Systems, 2006

2005
Security evaluation against electromagnetic analysis at design time.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

A Vector Approach to Cryptography Implementation.
Proceedings of the Digital Rights Management: Technologies, 2005

Self-Timed Circuitry for Global Clocking.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
Low-Latency Virtual-Channel Routers for On-Chip Networks.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Analog Micropipeline Rings for High Precision Timing.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Balanced self-checking asynchronous logic for smart card applications.
Microprocess. Microsystems, 2003

Security Evaluation of Asynchronous Circuits.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002
JMA: The Java-Multithreading Architecture for Embedded Processors.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Point to Point GALS Interconnect.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Improving Smart Card Security Using Self-Timed Circuits.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Protecting Consumer Security Devices.
Proceedings of the Smart Card Programming and Security, 2001

2000
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998
Rapid prototyping of self-timed circuits.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1995
Tagged Up/Down Sorter - A Hardware Priority Queue.
Comput. J., 1995


  Loading...