Gerard K. Rauwerda

According to our database1, Gerard K. Rauwerda authored at least 27 papers between 2003 and 2022.

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Bibliography

2022
Preventing Soft Errors and Hardware Trojans in RISC-V Cores.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2017
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
RQNoC: A Resilient Quality-of-Service Network-on-Chip with Service Redirection.
ACM Trans. Embed. Comput. Syst., 2016

A configurable SIMD architecture with explicit datapath for intelligent learning.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

2014

2013
Compiling Scilab to high performance embedded multicore systems.
Microprocess. Microsystems, 2013

DeSyRe: On-demand system reliability.
Microprocess. Microsystems, 2013

Software Modification Aided Transient Error Tolerance for Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

The DeSyRe Project: On-Demand System Reliability.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Multicore soc for on-board payload signal processing.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2008
Multi-standard adaptive wireless communication receivers: adaptive applications mapped on heterogeneous dynamically reconfigurable hardware.
PhD thesis, 2008

Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core.
Proceedings of the FPL 2007, 2007

2006
Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Hydra: An Energy-efficient and Reconfigurable Network Interface.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Reconfigurable Architectures for Adaptable Mobile Systems.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004
Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture.
J. Supercomput., 2004

Implementation of a HiperLAN/2 Receiver on the Reconfigurable Montium Architecture.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

BER Estimation for HiperLAN/2.
Proceedings of the Personal Wireless Communications, IFIP TC6 9th International Conference, 2004

Implementation of a flexible RAKE receiver in heterogeneous reconfigurable hardware.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2003
Mapping Wireless Communication Algorithms to a Reconfigurable Architecture.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003


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