Pengcheng Huang
Orcid: 0000-0001-8239-467XAffiliations:
- National University of Defense Technology, Microelectronics and Microprocessor Institute, Changsha, China
According to our database1,
Pengcheng Huang authored at least 9 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
2022
Experimental Investigation of Charge Sharing Induced SET Depending on Transistors in Abutted Rows in 65 nm Bulk CMOS Technology.
IEEE Access, 2022
2021
Symmetry, 2021
2018
Angular dependency on heavy-ion-induced single-event multiple transients (SEMT) in 65 nm twin-well and triple-well CMOS technology.
Microelectron. Reliab., 2018
2017
Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation.
Sci. China Inf. Sci., 2017
2016
Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology.
Sci. China Inf. Sci., 2016
2015
Single event transient propagation in dynamic complementary metal oxide semiconductor cascade circuits.
IEICE Electron. Express, 2015
IEICE Electron. Express, 2015
Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits.
Sci. China Inf. Sci., 2015