Yaohua Wang

Orcid: 0009-0004-7214-1176

According to our database1, Yaohua Wang authored at least 86 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

2023
A Survey of Memory-Centric Energy Efficient Computer Architecture.
IEEE Trans. Parallel Distributed Syst., October, 2023

Parallel incremental association rule mining framework for public opinion analysis.
Inf. Sci., June, 2023

Beyond Appearance: a Semantic Controllable Self-Supervised Learning Framework for Human-Centric Visual Tasks.
CoRR, 2023

Evaluating Autoencoders for Dimensionality Reduction of MRI-derived Radiomics and Classification of Malignant Brain Tumors.
Proceedings of the 35th International Conference on Scientific and Statistical Database Management, 2023

A Bitwise GAC Algorithm for Alldifferent Constraints.
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

Improving Prediction of Late Symptoms using LSTM and Patient-reported Outcomes for Head and Neck Cancer Patients.
Proceedings of the 11th IEEE International Conference on Healthcare Informatics, 2023

PrivNUD: Effective Range Query Processing under Local Differential Privacy.
Proceedings of the 39th IEEE International Conference on Data Engineering, 2023

Applying Binary Code Similarity Detection on Acceleration Processor.
Proceedings of the 4th International Conference on Computer Engineering and Intelligent Control, 2023

DAS: A DRAM-Based Annealing System for Solving Large-Scale Combinatorial Optimization Problems.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

DeTAR: A Decision Tree-Based Adaptive Routing in Networks-on-Chip.
Proceedings of the Euro-Par 2023: Parallel Processing - 29th International Conference on Parallel and Distributed Computing, Limassol, Cyprus, August 28, 2023

DeepMAD: Mathematical Architecture Design for Deep Convolutional Neural Network.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

Beyond Appearance: A Semantic Controllable Self-Supervised Learning Framework for Human-Centric Visual Tasks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

2022
Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.
IEEE Trans. Parallel Distributed Syst., 2022

Beyond Classifiers: Remote Sensing Change Detection with Metric Learning.
Remote. Sens., 2022

Mutual Information Learned Regressor: an Information-theoretic Viewpoint of Training Regression Systems.
CoRR, 2022

Robust Graph Structure Learning over Images via Multiple Statistical Tests.
CoRR, 2022

MT-3000: a heterogeneous multi-zone processor for HPC.
CCF Trans. High Perform. Comput., 2022

Robust Graph Structure Learning via Multiple Statistical Tests.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Ada-NETS: Face Clustering via Adaptive Neighbour Discovery in the Structure Space.
Proceedings of the Tenth International Conference on Learning Representations, 2022

Cost-Aware TVM (CAT) Tensorization for Modern Deep Learning Accelerators.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Work-in-Progress: RISC-V Based Low-cost Embedded Trace Processing System.
Proceedings of the International Conference on Compilers, 2022

2021
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks.
ACM Trans. Archit. Code Optim., 2021

Comparative study of electro-thermal characteristics of 4500 V diffusion-CS IGBT and buried-CS IGBT.
IET Circuits Devices Syst., 2021

Threshold-Based Hierarchical Clustering for Person Re-Identification.
Entropy, 2021

2nd Place Solution to Google Landmark Retrieval 2021.
CoRR, 2021

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework.
CoRR, 2021

Fine-Grained AutoAugmentation for Multi-Label Classification.
CoRR, 2021

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions.
CCF Trans. High Perform. Comput., 2021

CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework.
Proceedings of the Information Processing in Medical Imaging, 2021

Predicting late symptoms of head and neck cancer treatment using LSTM and patient reported outcomes.
Proceedings of the IDEAS 2021: 25th International Database Engineering & Applications Symposium, 2021

Temporal Convolutional Network Based Regression Approach for Estimation of Remaining Useful Life.
Proceedings of the International IEEE Conference on Prognostics and Health Management, 2021

Study on the influence of pressure on the characteristics of IGBT.
Proceedings of the EITCE 2021: 5th International Conference on Electronic Information Technology and Computer Engineering, Xiamen, China, October 22, 2021

Universal Pre-Calculating Structure: Reducing Complexity of Ising Chips with Arbitrary Connectivity.
Proceedings of the Sixth IEEE International Conference on Data Science in Cyberspace, 2021

HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Deviation based clustering for unsupervised person re-identification.
Pattern Recognit. Lett., 2020

Energy clustering for unsupervised person re-identification.
Image Vis. Comput., 2020

A Novel High Performance 6500V IGBT with P-type Schottky Contact.
Proceedings of the RICAI 2020: 2nd International Conference on Robotics, 2020

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A Macro-Micro Weakly-Supervised Framework for AS-OCT Tissue Segmentation.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020

Associative Thread Compaction for Efficient Control Flow Handling in GPGPUs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

A Comparative Study of Speculative Retrieval for Multi-Modal Data Trails: Towards User-Friendly Human-Vehicle Interactions.
Proceedings of the ICCAI '20: 2020 6th International Conference on Computing and Artificial Intelligence, 2020

An In-depth Analysis of System-level Techniques for Simultaneous Multi-threaded Processors in Clouds.
Proceedings of the HP3C 2020: 4th International Conference on High Performance Compilation, 2020

Simulation optimization and Verification of edge terminations for high voltage IGBTs.
Proceedings of the EITCE 2020: 4th International Conference on Electronic Information Technology and Computer Engineering, Xiamen, China, 6 November, 2020, 2020

Hierarchical Clustering With Hard-Batch Triplet Loss for Person Re-Identification.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

A Lifelong Health Monitoring Framework in Processors: Work-in-Progress.
Proceedings of the International Conference on Compilers, 2020

2019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units.
ACM Trans. Archit. Code Optim., 2019

Finer Resolution Mapping of Marine Aquaculture Areas Using WorldView-2 Imagery and a Hierarchical Cascade Convolutional Neural Network.
Remote. Sens., 2019

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.
CoRR, 2019

The Evaluation of DCNN on Vector-SIMD DSP.
IEEE Access, 2019

A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model.
IEEE Access, 2019

Succinct Representations in Collaborative Filtering: A Case Study using Wavelet Tree on 1, 000 Cores.
Proceedings of the 20th International Conference on Parallel and Distributed Computing, 2019

2018
Advancing CMOS-Type Ising Arithmetic Unit into the Domain of Real-World Applications.
IEEE Trans. Computers, 2018

Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions.
CoRR, 2018

Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Pre-Calculating Ising Memory: Low Cost Method to Enhance Traditional Memory with Ising Ability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: Image Segmentation on the FPGA-based Pre-calculating Ising Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2016
Iteration Interleaving-Based SIMD Lane Partition.
ACM Trans. Archit. Code Optim., 2016

Multi-bit transient fault control for NoC links using 2D fault coding method.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
B-SCT: Improve SpMV processing on SIMD architectures.
IEICE Electron. Express, 2015

2014
FT-Matrix: A Coordination-Aware Architecture for Signal Processing.
IEEE Micro, 2014

2013
Research on Social Network Structure and Public Opinions Dissemination of Micro-blog Based on Complex Network Analysis.
J. Networks, 2013

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures.
IEICE Trans. Inf. Syst., 2013

Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors.
IEICE Electron. Express, 2013

A novel QPP interleaver for parallel turbo decoder.
IEICE Electron. Express, 2013

Redefining the relationship between scalar and parallel units in SIMD architectures.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.
IEICE Electron. Express, 2012

A cost conscious performance model for media processors.
IEICE Electron. Express, 2012

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures.
IEEE Comput. Archit. Lett., 2012

Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Architectural Implications for SIMD Processors in the Wireless Communication Domain.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011
LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.
IEICE Electron. Express, 2011

SUCA: a scalable unicore architecture with novel instruction encoding and distributed execution control.
IEICE Electron. Express, 2011

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

AIFSP: An Adaptive Instruction Flow Stream Processor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010


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