Shuming Chen

According to our database1, Shuming Chen authored at least 104 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Novel DSP Architecture for Scientific Computing and Deep Learning.
IEEE Access, 2019

The Evaluation of DCNN on Vector-SIMD DSP.
IEEE Access, 2019

A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model.
IEEE Access, 2019

2018
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Advancing CMOS-Type Ising Arithmetic Unit into the Domain of Real-World Applications.
IEEE Trans. Computers, 2018

Pre-Calculating Ising Memory: Low Cost Method to Enhance Traditional Memory with Ising Ability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Live Demonstration: Image Segmentation on the FPGA-based Pre-calculating Ising Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Background of Semantic Intelligence Research and the Principle of Technical Framework.
Proceedings of the Cognitive Systems and Signal Processing - 4th International Conference, 2018

Fast automatic generation of efficient custom instructions for application-aware computing.
Proceedings of the Tenth International Conference on Advanced Computational Intelligence, 2018

2017
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.
ACM Trans. Embedded Comput. Syst., 2017

Modeling the impact of process and operation variations on the soft error rate of digital circuits.
Sci. China Inf. Sci., 2017

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation.
Sci. China Inf. Sci., 2017

A high-speed low voltage CMOS Schmitt Trigger with adjustable hysteresis.
Proceedings of the 16th IEEE/ACIS International Conference on Computer and Information Science, 2017

2016
A Novel Layout-Based Single Event Transient Injection Approach to Evaluate the Soft Error Rate of Large Combinational Circuits in Complimentary Metal-Oxide-Semiconductor Bulk Technology.
IEEE Trans. Reliability, 2016

Iteration Interleaving-Based SIMD Lane Partition.
TACO, 2016

Characterization of the field-dependent permittivity of Ba0.5Sr0.5TiO3 thin films up to 110 GHz.
IEICE Electronic Express, 2016

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology.
Sci. China Inf. Sci., 2016

A Radiation Hardening Algorithm on 2nd Order CDR.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

2015
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
JSW, 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electr. Comput. Eng., 2015

Single event transient propagation in dynamic complementary metal oxide semiconductor cascade circuits.
IEICE Electronic Express, 2015

Propagation-constant matching based broadband permittivity extraction from S-parameter.
IEICE Electronic Express, 2015

Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes.
IEICE Electronic Express, 2015

Flip-flops soft error rate evaluation approach considering internal single-event transient.
Sci. China Inf. Sci., 2015

Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits.
Sci. China Inf. Sci., 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A novel method to reduce ancilla and garbage bits of reversible quantum multipliers.
Proceedings of the 11th International Conference on Natural Computation, 2015

2014
FT-Matrix: A Coordination-Aware Architecture for Signal Processing.
IEEE Micro, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electronic Express, 2014

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology.
Sci. China Inf. Sci., 2014

Implementation of a dynamic wordlength SIMD multiplier.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

2013
Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells.
Microelectron. J., 2013

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures.
IEICE Trans. Inf. Syst., 2013

Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors.
IEICE Electronic Express, 2013

Decoupled iteration mapping: improving dependency-loop performance on SIMD processors.
IEICE Electronic Express, 2013

A novel QPP interleaver for parallel turbo decoder.
IEICE Electronic Express, 2013

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Comput. Electr. Eng., 2013

A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors.
Proceedings of the Network and Parallel Computing - 10th IFIP International Conference, 2013

Redefining the relationship between scalar and parallel units in SIMD architectures.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism.
Microelectron. Reliab., 2012

CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.
IEICE Electronic Express, 2012

Erratum: Control-enhanced power-SIMD [IEICE Electronics Express Vol.9 (2012), No 14 pp 1147-1152].
IEICE Electronic Express, 2012

Control-enhanced power-SIMD.
IEICE Electronic Express, 2012

A cost conscious performance model for media processors.
IEICE Electronic Express, 2012

A novel parallel memory organization supporting multiple access types with matched memory modules.
IEICE Electronic Express, 2012

Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process.
Sci. China Inf. Sci., 2012

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures.
IEEE Comput. Archit. Lett., 2012

The existence of doubly disjoint (mt+1, m, m-1) difference families.
Ars Comb., 2012

Study of rough surface to decrease reverberation noise in ultrasonic imaging.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Architectural Implications for SIMD Processors in the Wireless Communication Domain.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Preprocessing Scheme of Intelligent Assembly for a High Performance VLIW DSP.
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

2011
Hybrid Distributed Shared Memory Space in Multi-core Processors.
JSW, 2011

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.
IEICE Electronic Express, 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.
IEICE Electronic Express, 2011

SUCA: a scalable unicore architecture with novel instruction encoding and distributed execution control.
IEICE Electronic Express, 2011

DSBS: Distributed and Scalable Barrier Synchronization in Many-Core Network-on-Chips.
Proceedings of the IEEE 10th International Conference on Trust, 2011

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

AIFSP: An Adaptive Instruction Flow Stream Processor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and chip implementation of a heterogeneous multi-core DSP.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the Manycore Era.
IEEE Trans. Circuits Syst. Video Techn., 2010

YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP.
J. Comput. Sci. Technol., 2010

A coprocessor for real-time motion estimation in HD video coding.
Proceedings of the Visual Communications and Image Processing 2010, 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC.
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.
Proceedings of the Third International Symposium on Parallel Architectures, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.
Proceedings of the Design, Automation and Test in Europe, 2010

PPTWO: Push-Pull cell based Traveling Wave Oscillator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Oscillation of second-order functional differential equations with mixed nonlinearities and oscillatory potentials.
Appl. Math. Comput., 2009

The existence of (v, 4, λ) disjoint difference families.
Australas. J Comb., 2009

Combinational logic SER estimation with the presence of re-convergence.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Nonoscillatory solutions of second order nonlinear difference equations.
Appl. Math. Comput., 2008

An Efficient Parallel Algorithm for H.264/AVC Encoder.
Proceedings of the Ninth International Conference on Parallel and Distributed Computing, 2008

Efficient Bit-Rate Estimation for Mode Decision of H.264/AVC.
Proceedings of the Image Analysis and Recognition, 5th International Conference, 2008

Analysis of Glitch Reconvergence in Combinational Logic SER Estimation.
Proceedings of the Second Asia International Conference on Modelling and Simulation, 2008

Fast and Accurate Estimate SET Voltage Pulses from Transient Currents Induced by Heavy Ion.
Proceedings of the Second Asia International Conference on Modelling and Simulation, 2008

The design and algorithm mapping of a heterogeneous multi-core processor for SDR.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Efficient bit-rate estimation technique for CABAC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

SPVA: A novel digital signal processor architecture for Software Defined Radio.
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007
Applications of On-chip Trace on Debugging Embedded Processor.
Proceedings of the 8th ACIS International Conference on Software Engineering, 2007

An On-Line Control Flow Checking Method for VLIW Processor.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

M2SI: An Improved Coherency Protocol in CMP.
Proceedings of the International Conference on Networking, 2007

Lidar application in selection and design of power line route.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2007

Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition.
Proceedings of the High Performance Computing and Communications, 2007

FROCM: A Fair and Low-Overhead Method in SMT Processor.
Proceedings of the High Performance Computing and Communications, 2007

A DRAM Precharge Policy Based on Address Analysis.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Exploiting Thread-Level Parallelism of Irregular LDPC Decoder with Simultaneous Multi-threading Technique.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Pseudo Share Data Cache in Multiprocessor: PSDMP.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

MID: a Novel Coherency Protocol in Chip Multiprocessor.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006


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