Peter Bellows

According to our database1, Peter Bellows authored at least 10 papers between 1998 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2005
High-Visibility Debug-By-Design for FPGA Platforms.
J. Supercomput., 2005

2004
Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
IPsec-Protected Transport of HDTV over IP.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Applications of adaptive computing systems for signal processing challenges.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512.
Proceedings of the Information Security, 5th International Conference, 2002

GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Designing Run-Time Reconfigurable Systems with JHDL.
J. VLSI Signal Process., 2001

Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board.
Proceedings of the Information Security, 4th International Conference, 2001

1999
A CAD Suite for High-Performance FPGA Design.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
JHDL - An HDL for Reconfigurable Systems.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998


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